Abstract: In a delta sigma modulator, generally comprising one or more integrators fed into a multilevel quantizer, the output of which is the output of the delta sigma modulator and is also fed through a digital to analog converter in a feedback loop to the integrators, the quantizer is made sparse, i.e. the levels output by the quantizer are not evenly spaced, but rather are closely spaced for small deviations from 0 V, and broadly spaced for large deviations from 0V. The A/D converter in the feedback is matched to the quantizer. For example, the levels might be -1 V, -1/8 V, 0V, 1/8 V, and 1 V. The digital output signal from the sparse quantizer is fed into a correction RAM, which corrects for nonlinearities in the D/A converter before the digital signal is filtered by a low pass filter and frequency down converted. The contents of the RAM are selected whenever the A/D conversion system is powered on.

Abstract: A preadder for a multiplier integrates a pre-adder and Booth encoder. The integrated pre-adder/Booth encoder comprises multiple stages, each of which adds and encodes multiple bits (usually two) of two numbers x and y. Each stage comprises three blocks, a first carry generation block, a second carry generation block, and an output code generation block. The x input bits and y input bits are input into the first carry block, which generates a first carry out and multibit combination signal, which generally comprises the x input bits and y input bits carried straight through or only slightly modified. The combination signal and a first carry in signal are inputs to the second carry generation block. Generally, the first carry in is the is the first carry out of another stage which is combining less significant bits than the present stage. The second carry generation block generates a second carry out signal and a sum signal.