Abstract: A local buffer is integrated with a witness generator and a proof generator on a cryptographic processor and is separate from host memory accessed by a host processor operating with the cryptographic processor in a proving computing system. The witness generator: receives, from software program running on the host processor, compiled code of a zero-knowledge-proof (ZKP) program and specific input to the ZKP program; executes the ZKP program by way of executing the compiled code; records specific output generated from the ZKP program with the specific input, intermediate variable values, and the specific input, as a specific witness of executing the ZKP program; stores the specific witness in the local buffer. The proof generator: receives, from the software program running on the host processor, a proving key; accesses the specific witness in the local buffer; generates a specific zero-knowledge proof for executing the ZKP program with the specific input.

Abstract: An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Abstract: An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip determines whether the bus is in a busy state or an idle state. If the IC chip determines that the bus is in the idle state, the IC chip blocks communication from upstream chips on the bus, and transmit data on the bus. If the IC chip determines that the bus is in the busy state, the IC chip delays transmitting the data on the bus for a delay period, and transmits its data on the bus if the bus is determined to be in the idle state upon expiry of the delay period.

Abstract: Some aspects of the present disclosure involve a method including: receiving instructions specifying a particular site from among a plurality of sites, wherein each of the plurality of sites comprises one or more computing devices, each of the one or more computing devices comprising a plurality of integrated circuit (IC) chips that are configured to perform similar computations in parallel; and in response to receiving the instructions, performing a firmware upgrade for each of the one or more computing devices at the particular site.

Abstract: Examples of devices for providing cooling solutions are described. One example device includes a boilerplate, a printed circuit board (PCB), one or more integrated circuit (IC) chips placed on the PCB, a thermal interface material (TIM), and one or more gaskets. The TIM is placed between the boilerplate and at least one IC chip of the one or more IC chips. The TIM is coupled to a surface of at least the IC chip that faces the boilerplate. The one or more gaskets are placed between the boilerplate and the PCB and encompassing the TIM. The one or more gaskets are configured to seal the at least one IC chip to provide a protective barrier for the TIM.

Abstract: A system with a switching device is presented. The switching device includes first ports which interconnect first processing units in a first group using a first protocol and includes second ports which interconnect the first processing units with second processing units amongst second groups using the first protocol in conjunction with a second protocol. The switching device includes a switching fabric which determines a destination of an incoming data unit. If the destination is determined to be a first processing unit in the first group, the switching fabric forwards the data unit to a first port of the first ports using the first protocol. If the destination is determined to be a second processing unit in a second group of the second groups, the switching fabric forwards the data unit to a second port of the second ports using the first protocol in conjunction with the second protocol.

Abstract: A method includes: obtaining a site-specific power plan for a first site, wherein the first site includes a plurality of computing devices that are configured to receive power through a common grid-facing meter; obtaining a first group-specific objective for a first group of computing devices of the plurality of computing devices, and obtaining a second group-specific objective for a second group of computing devices of the plurality of computing devices; determining computational parameters of the plurality of computing devices based on the first group-specific objective and the second group-specific objective, subject to one or more constraints corresponding to the site-specific power plan; and controlling the plurality of computing devices to perform the common type of computation using the determined computational parameters.

Abstract: In an example method, a computer system accessing first natural language user input representing a request to generate security policies for a computerized security platform, and generates the security policies using a computerized large language model (LLM). Generating the one or more security policies includes determining an identity of the computerized security platform, providing at least a portion of the first natural language user input and the identity of the computerized security platform to the LLM, and receiving, from the LLM, first output data representing the security policies. The first output data has a computer language syntax that is compatible with the computerized security platform. Further, the system causes the security policies to be presented to a user and to be stored on a computerized storage device.

Abstract: An example system, includes clock synchronization circuitry, first data processing circuitry, and second data processing circuitry electrically coupled to the clock synchronization circuitry and the first processing circuitry. The clock synchronization circuitry is configured to receive a first signal, and output a second signal synchronized to a clock domain of the second data processing circuitry. The first data processing circuitry is configured to perform one or more first computations based on the first signal, and provide, to the second data processing circuitry, a result corresponding to the one or more first computations. The second data processing circuitry is configured to perform one or more second computations based on the second signal, determine whether the one or more second computations satisfies a selection criterion, and generate output data representing whether the one or more second computations satisfies the selection criterion.

Abstract: A system that includes a control system communicatively coupled to at least one computation hardware asset through one or more networks. The control system is configured to present on a user interface, a digital map including icons indicating individual IC chips on a circuit board of the computation hardware asset. The icons are arranged on the digital map corresponding to physical locations of the individual IC chips. The control system is further configured to: receive a value of a parameter of at least one of the individual IC chips via the one or more networks; based on the received value, select a category for the received value from a group of possible categories; and present, associated with the icon of the at least one of the individual IC chips on the digital map, information indicating the category for the received value.

Abstract: An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip performs a combining operation and an inverting operation on a signal produced by the IC chip and the input signal to generate an output signal. The IC chip sends the output signal to a next chip of the number of IC chips on the bus.

Abstract: A circuit system includes: a plurality of integrated circuit (IC) chips on a circuit board; a first conduit configured to convey a first flow of a coolant, wherein the first conduit is arranged such that the first flow of the coolant through the first conduit cools the circuit board; a second conduit configured to convey a second flow of the coolant from a common inlet with the first conduit, wherein the second flow bypasses the first conduit; a valve configured to adjust a relative degree of flow of the coolant between the first conduit and the second conduit; and a controller configured to, based at least on data characterizing operation of the plurality of IC chips, control the valve to adjust a first flow rate of the coolant through the first conduit.

Abstract: A system includes a plurality of computing devices. Each of the plurality of computing devices includes a plurality of integrated circuit (IC) chips configured to perform a common type of computation in parallel with one another. At least one of the plurality of computing devices is configured to: receive event data providing a target time of a power event, and a time interval; determine a random time within a time range, wherein the time range is based on the target time and the time interval; determine that a current time has reached the target time; and, based on determining that the current time has reached the target time, switch one or more of the plurality of IC chips corresponding to the computing device from a first power mode to a second power mode at the random time.

Abstract: A computing device includes: a plurality of integrated circuit (IC) chips arranged on one or more substrates; and a controller. The controller is configured to: control the plurality of integrated circuit (IC) chips to perform a common type of computation in parallel with one another; receive, from one or more of the plurality of IC chips, IC chip data indicative of performance of the IC chips; generate status data based on the IC chip data; and push the status data to a remote asset management server.

Abstract: A system includes a plurality of computing devices. Each of the plurality of computing devices includes a plurality of integrated circuit (IC) chips configured to perform a common type of computation in parallel with one another. At least one of the plurality of computing devices is configured to: receive, from an asset management server, an event data providing target values for one or more parameters to schedule a power event; store the event data in a storage coupled to the computing device; monitor one or more current values for the one or more parameters; and, based on determining that the current values for the one or more parameters have reached the target values, switch one or more of the plurality of IC chips corresponding to the computing device from a first power mode to a second power mode.

Abstract: A security gateway accesses data in a communications session between a client device and an application hosted by a server. The security gateway inspects security parameters corresponding to the data using one or more large language models (LLMs). In response to inspecting the security parameters corresponding to the data, the security gateway performs one or more security operations on the data in accordance with one or more security policies associated with the one or more LLMs.

Abstract: An electronic system for calculating and mining digital currency using circuits optimized for efficient utilization of hash engine circuitry by determining an effective hash clock operational frequency for one or more hash engines in the system. The hash engines can be evaluated to determine a maximum operational frequency for a given error threshold. The hash engines can also be partitioned into one or more hash engine groups to allow different groups to operate at different overclocked frequencies.

Abstract: A method includes detecting, by an electronic device managing a plurality of integrated circuit (IC) chips, an attempt to modify a whitelist that includes multiple entries of URLs and user IDs and determining whether the attempt is associated with modifying an existing entry, removing the existing entry, or adding a new entry of a URL or a user ID to the whitelist. When the attempt is associated with removing an existing entry corresponding to a particular URL or user ID, the method includes further determining whether the particular URL or user ID is being actively used by IC chip(s). When the attempt to modify or remove the existing entry or add a new entry of a URL or user ID to the whitelist is approved, a notification is transmitted to an electronic communication channel associated with a root administrator and pool managing administrators that manage one or more pool servers.

Abstract: Some aspects of the present disclosure involve an apparatus including: a sensor mounted on an electronic device submerged in a cooling fluid in an immersion tank. The sensor includes circuitry configured to: measure a value of a capacitance of the cooling fluid; and transmit the measured value of the capacitance to a controller device that is communicatively coupled to the at least one sensor. The controller device including one or more processors and configured to: receive the measured value of the capacitance from the at least one sensor; determine that the measured value of the capacitance is less than a threshold value; determine that a fluid level of the cooling fluid in the immersion tank is below a threshold level; and perform a remedial action in response to determining that the fluid level of the cooling fluid in the immersion tank is below the threshold level.

Abstract: A circuit board assembly is provided. The circuit board assembly includes a circuit board and a plurality of chips assembled on a surface of the circuit board. The plurality of chips include integrated circuit (IC) chips. At least two chips are positioned on the surface of the circuit board adjacent to one another with a spacing separating the two chips that is less than a minimum dimension of each of the two chips. A circuit board and a method for circuit board assembly are also provided.