Abstract: A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks.
Type:
Grant
Filed:
December 5, 1997
Date of Patent:
June 27, 2000
Assignee:
Auspex Systems, Incorporated
Inventors:
Paul Popelka, Tarun Kumar Tripathy, Richard Allen Walter, Paul Brian Del Fante, Murali Sundaramoorthy Repakula, Lakshman Narayanaswamy, Donald Wayne Sterk, Amod Prabhakar Bodas, Leslie Thomas McCutcheon, Daniel Murray Jones, Peter Kingsley Craft, Clive Mathew Philbrick, David Allan Higgen, Edward John Row