Abstract: A low phase jitter oscillator which is adjustable in frequency is disclosed. The oscillator comprises a logical OR gate having a feedback loop adjustable in length between the inverted output of the gate and the input of the gate. Using this configuration, the output changes state once every 1/2 T seconds wherein 1/2 T is equal to the propagation delay through the feedback loop and the OR gate. The frequency of the oscillator can be adjusted by adjusting the length of the feedback loop which correspondingly modifies the propagation delay through the feedback loop and thus the frequency of the oscillator output.

Abstract: A container for housing electrical apparatus is described. The container has a front panel with affixation means and handles that can be secured for transportation. The front panel can also be opened for access to the internal apparati. The side panels are integrated and reinforced to protect the internal apparati. A connection board is provided to aid in inter connecting the internal apparati. A hinge means is disclosed that allows for self-alignment of the affixation means. Hanger bars are provided for mounting the container on mounting frames. A back panel can also be used during transportation to protect the connection board.

Abstract: A high speed bus structure and data transfer method to provide data transfer capability between a central processing device and a plurality of electrical modules coupled to the bus. In the preferred embodiment, a central processing unit is coupled to a plurality of electrical modules for data reception and transmission. In a module "listen" cycle, the central processor (CP) device generates a function code which is transmitted on a command bus coupled to each electrical module. The CP device asserts data required by the particular module function on the data bus coupled to each electrical module. The CP device transmits an enable signal (ES) on an enable bus to enable the particular electrical module which is to receive data and asserts a clock signal on a clock line coupled to each module. The enabled electrical module receives valid data from the CP device upon sensing a deasserted clock line denoting the end of a clock cycle.

Abstract: A display control circuit for automatically displaying a sampled test signal on a CRT display, or the like, where the test signal is received at an unknown period following a trigger. The circuit first establishes a base line referenced level, then the sampling of the test signal is controlled by a varied pedestal voltage or counter potential until the magnitude of the sampled test signal exceeds the base line reference level by a predetermined potential. The pedestal voltage or counter potential required to establish this predetermined potential is used for delaying the start of the display sweep following the trigger.