Abstract: A method and apparatus for state assignment of a logic circuit comprises receiving internal state representations for the logic circuit, determining binary code for the internal state representations by successively dividing the states into disjoint sets of ever decreasing size Each disjoint set of a pair is assigned a one bit at each division step. The division can continue for all bits to be encoded, or the division can be halted and exact encoding used for the encoding of the final number of bits.

Abstract: A method of designing a cascade decomposed sequential circuit is described in which an input state graph for a sequential circuit is used to generate functions defining transitions between states of the sequential circuit. These functions are used to generate sets of states of the sequential circuit and which contain possible states of the sequential circuit. Levels are then assigned to the generated sets and states are assigned to sequential circuit components in accordance with the assigned levels. These assigned states comprise the current states of the sequential circuit components and using these states and the functions, next states for these sequential circuit components are derived.