Patents Assigned to Avago Technologies
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Patent number: 12382491Abstract: In some aspects, the disclosure is directed to methods and systems for early termination of multi-user enhanced distributed channel access parameter application for one or more stations or devices. In various implementations, referred to as un-solicited or solicited termination, the multi-user enhanced distributed channel access timeout period may be terminated early by an access point device, or by a non-access point station or device, respectively.Type: GrantFiled: August 8, 2023Date of Patent: August 5, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhou Lan, Chunyu Hu
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Patent number: 12381752Abstract: In some aspects, the disclosure is directed to methods and systems for interference mitigation and cancellation in full duplex amplifiers for cable modem or broadband communication systems. In many implementations, an interference canceller in the downstream path may be provided to equalize composite power on the FDX upstream subbands within a predetermined range of amplitude (e.g. X dB) from the desired downstream signal on the same subband, without affecting the downstream subbands.Type: GrantFiled: May 24, 2022Date of Patent: August 5, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Avi Kliger, Niki Pantelias, Hagay Garti, Anatoli Shindler
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Publication number: 20250244486Abstract: Technical solutions improve GNSS receiver performance by combining pilot and data components of the GNSS signal to enhance the accuracy of a DLL, PLL or FLL of the receiver. A receiver receives a GNSS signal, removes a carrier component and provides in-phase and quadrature data and pilot signals. Data circuits can process the in-phase and quadrature data signals for data early and date late offsets and pilot circuits can process the in-phase and quadrature pilot signals for pilot early and pilot late offsets. The data early and data late signals can be combined to provide a data error difference and pilot early and pilot late signals can be combined to provide a pilot error difference. A summing circuit can combine pilot and data error differences to provide a delay lock loop (DLL) error signal.Type: ApplicationFiled: April 30, 2024Publication date: July 31, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Premal Harish Madhani, Chi Nee, Charles Raymond Abraham
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Publication number: 20250247907Abstract: A technical solution for band steering of WLAN traffic using multi-link operation is provided. The solution can include a multi-link device (MLD) to establish a multi-link (ML) comprising links across different frequency bands. The MLD can grant a device to share access to a link of the ML with a WLAN device. The device can communicate using a different type of wireless protocol than a protocol of the WLAN device sharing a frequency band with the device. The MLD can block a WLAN communication of the WLAN device on the link of the ML to be used by device for communicating and direct WLAN transmissions to a non-shared link of the ML while the device performs activity (e.g., other than WLAN communication) on the link. The MLD can allow the WLAN device to resume WLAN transmission on the link responsive to the device completing activity on the link.Type: ApplicationFiled: July 23, 2024Publication date: July 31, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Peyush AGARWAL, Namit GARG, Bobby JOSEPH, Pradhap ASOKAN
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Publication number: 20250247106Abstract: A system includes an amplifier to receive a signal, an analog-to-digital converter (ADC), a first switch coupled to a capacitor to receive an output from the amplifier, the capacitor to provide the output to the ADC, a second switch coupled between the capacitor and the ADC to turn on/off the ADC, a third switch coupled between the amplifier and the first switch to connect/disconnect the output to/from the first switch, a fourth switch coupled between the amplifier and the first switch to bypass the amplifier, and circuitry. The circuitry turns on the first switch and the second switch to initiate charging the capacitor, turns on the fourth switch and turns off the third switch to complete the charging, and turns off the second switch and the first switch to control the ADC to convert the output to a digital signal.Type: ApplicationFiled: January 29, 2024Publication date: July 31, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Gen Qu, Hans Eberhart
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Patent number: 12374984Abstract: A controller includes a first circuit that receives first and second input signals and generates an output pulse based on the first and second input signals. A timer circuit of the controller generates the first input signal for the first circuit. A second circuit of the controller generates the second input signal for the first circuit. In response to the second input signal being set to a first value, smaller than a second value, the first circuit sets the output pulse to the second value and start a first duration. In response to the second input signal being set to the second value and the first input signal changing from the first value to the second value, the first circuit sets the output pulse to the first value to end the first duration and start a second duration such that the second duration is maintained more than a time limit.Type: GrantFiled: February 21, 2023Date of Patent: July 29, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Shengyuan Li, Xicheng Jiang, Kareem Abdelghani Ibraheem Mohamed Ragab, Zen Wu
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Patent number: 12366961Abstract: Solutions for managing RAID virtual disks. Some solutions enable increased use of hardware circuitry to schedule and perform IO on a virtual drive, providing for more efficient IO. In some cases, this can be accomplished by notifying the hardware of precise regions of a virtual disk affected by the maintenance operation and any given time. The hardware then, can continue to perform host IO on portions of the logical disk not undergoing maintenance.Type: GrantFiled: October 30, 2023Date of Patent: July 22, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventor: Arun Prakash Jana
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Patent number: 12368440Abstract: Systems and methods relate a device for monitoring or tracking clock frequency. The device can include a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal, and a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal is indicative of a second number of cycles of the sample clock signal occurring during the first number of cycles of the reference clock signal. The device can also include a third circuit configured to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal using the second signal.Type: GrantFiled: April 27, 2023Date of Patent: July 22, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventor: Renfei Liu
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Patent number: 12369238Abstract: An apparatus includes a digital ramp generator comprising a delay line, the delay line comprising one or more delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on respective outputs of the one or more delay elements, a digital to analog converter coupled to the digital ramp generator, wherein the digital to analog converter is configured to generate a reference signal, wherein the reference signal is generated based, at least in part, on the code, and a driver coupled to the digital to analog converter, the driver configured to generate a drive current based, at least in part, on the reference signal.Type: GrantFiled: January 31, 2023Date of Patent: July 22, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Junjie Lu, Jingbo Duan, Jing Guo, Jianhua Gan, Jungwoo Song, Xicheng Jiang
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Publication number: 20250234372Abstract: Technical solutions provide setup sequences for multi access point (AP) coordinated beamforming (CBF) at a transmission opportunity (TXOP) stage. A first AP can transmit, to a second AP capable of participating in CBF and a first station of the first AP, a notification indicative of a CBF TXOP. The first AP can receive, from at least the first station, responsive to the notification, a first response identifying a first capability of the first station. The first AP can receive, from the second AP associated with a second one or more stations, responsive to the notification, a second response identifying a second capability of at least one of the second AP or a second station of the second one or more stations. The first AP can communicate data to the first station during the CBF TXOP according to at least one of the first capability or the second capability.Type: ApplicationFiled: October 31, 2024Publication date: July 17, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Srinath PUDUCHERI SUNDARAVARADHAN, Matthew J. FISCHER, George D. KONDYLIS, Hang SU, Ron PORAT, Sindhu VERMA, Shubhodeep ADHIKARI, Lekun LIN
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Publication number: 20250233619Abstract: Technical solutions include systems and methods for multi-access-point (AP) coordination of coordinated beamforming (CBF) for nulling of mutual interferences. A first AP can be configured to identify a second AP that is capable of participating in coordinated beamforming (CBF), select one or more candidate stations of the first AP and identify capabilities of at least one of the first AP or the one or more candidate stations. The first AP can be configured to determine one or more stations of the one or more candidate stations to participate in CBF based at least on the capabilities and perform a sequence with the second AP to exchange, between the first AP and the second AP, a set of stations of the first AP and the second AP to participate in CBF. The first AP can identify to the second AP the determined one or more stations as participating in CBF.Type: ApplicationFiled: October 31, 2024Publication date: July 17, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Srinath PUDUCHERI SUNDARAVARADHAN, Matthew J. FISCHER, George D. KONDYLIS, Hang SU, Ron PORAT, Sindhu VERMA, Shubhodeep ADHIKARI, Lekun LIN
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Publication number: 20250234381Abstract: The technical solutions are directed to coordinated beamforming per-TXOP frame sequence negotiation. A first access point (AP) can transmit, to a second AP and a first candidate set of stations, a first message to initiate transmission opportunity (TXOP) and a CBF request. The second AP can transmit a second message to a second candidate set of stations of the second AP identified to participate in the TXOP with a CBF response responsive to the CBF request. The first AP, responsive to receiving the CBF response, can transmit to the second AP a third message having a CBF trigger comprising information to synchronize a CBF transmission to be communicated during the TXOP.Type: ApplicationFiled: January 7, 2025Publication date: July 17, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Srinath PUDUCHERI SUNDARAVARADHAN, Matthew J. FISCHER, George D. KONDYLIS, Hang SU, Ron PORAT, Sindhu VERMA, Shubhodeep ADHIKARI, Lekun LIN
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Publication number: 20250233621Abstract: Technical solutions providing setup sequences for multi-access point (AP) coordinated beamforming (CBF). A system can include a first access point (AP) configured to transmit, to a second AP that is capable of participating in coordinated beamforming (CBF), a first notification frame comprising a first set of stations of the first AP to participate in a CBF transmission. The first AP can be configured to receive, from the second AP, responsive to the first notification frame, a first response frame comprising a second set of stations of the second AP to participate in the CBF transmission. The first AP can be configured to transmit data in the CBF transmission to at least one station of the first set of stations or the second set of stations, responsive to the first response frame.Type: ApplicationFiled: October 31, 2024Publication date: July 17, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Srinath PUDUCHERI SUNDARAVARADHAN, Matthew J. FISCHER, George D. KONDYLIS, Hang SU, Ron PORAT, Sindhu VERMA, Shubhodeep ADHIKARI, Lekun LIN
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Publication number: 20250234382Abstract: At least one aspect of the technical solutions can be directed to a system. The system can include a first access point (AP) that can be configured to transmit, to a second AP that can be capable of participating in coordinated beamforming (CBF) and a first candidate set of stations of the first AP, a first message to initiate transmission opportunity (TXOP). The second AP can be configured to transmit a second message to the first AP and a second candidate set of stations of second AP identified to participate in the TXOP. The second AP can be configured to transmit a third message having a CFB response to the first AP. The first AP can be configured to transmit a fourth message to second AP having a CBF trigger that can include information on a preamble of a CBF transmission to be communicated during the TXOP.Type: ApplicationFiled: January 7, 2025Publication date: July 17, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Srinath PUDUCHERI SUNDARAVARADHAN, Matthew J. FISCHER, George D. KONDYLIS, Hang SU, Ron PORAT, Sindhu VERMA, Shubhodeep ADHIKARI, Lekun LIN
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Publication number: 20250233688Abstract: A system may include a transmitter and one or more processors. The one or more processors may be configured to identify a number of additional symbols to be added to existing symbols corresponding to payload data to be encoded. The one or more processors may be configured to calculate, based on a length of the payload data and the number of additional symbols, a number of available bits for error correction. The one or more processors may be configured to encode, via an low-density parity-check (LDPC) encoder, the payload data using an LDPC code to generate a codeword having a number of parity bits corresponding to the available bits. The one or more processors may be configured to transmit, via the transmitter, the encoded data.Type: ApplicationFiled: April 29, 2024Publication date: July 17, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Andrew Blanksby, Rethnakaran Pulikkoonattu, Jun Zheng, Ron Porat, Vinko Erceg
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Patent number: 12362722Abstract: A resonator may include a first electrode, a second electrode, and a piezoelectric material between the first electrode and the second electrode, where the piezoelectric material is formed by fabricating the piezoelectric material with a compression axis vector (C-axis vector) oriented along a first direction and applying an electric field across the piezoelectric material to modify a direction of the C-axis vector to be oriented along a second direction. The second direction may be antiparallel to the first direction.Type: GrantFiled: July 20, 2022Date of Patent: July 15, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Paul Bradley, Richard Ruby, Reed Parker, Donald E. Lee
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Patent number: 12362773Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.Type: GrantFiled: April 29, 2022Date of Patent: July 15, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Xiaochen Yang, Hamid Hatamkhani, Guansheng Li, Yong Liu, Delong Cui, Jun Cao
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Patent number: 12360937Abstract: A Compute Express Link™ (CXL) over Ethernet (COE) station is provided to bridge a CXL fabric and an Ethernet network to allow for efficient native memory load/store access to remotely connected resources. The COE station supports CXL and Ethernet traffic through its CXL interface, scheduler/packers, decoders, VOQs and VIQs by adding COE tags to Ethernet frames. In CXL controller mode, the CXL controller drives the VOQs. In Ethernet mode, the COE module drives the VOQs, and interacts with the MAC sublayer and the PMA sublayer, which are responsible for encoding and decoding data signals for transmission through a serializer/deserializer.Type: GrantFiled: June 6, 2023Date of Patent: July 15, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Shreyas Shah, Jeffrey S. Earl, Anant Thakar, Sagar Borikar
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Patent number: 12353239Abstract: A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.Type: GrantFiled: June 23, 2023Date of Patent: July 8, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Tim Yee He, Siavash Fallahi, Zhi Chao Huang, Ali Nazemi, Jun Cao
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Ultra-compact and micropower circuit to monitor process, voltage, and temperature with high accuracy
Patent number: 12352807Abstract: A device includes a circuit that generates a first current associated with a voltage of a region of a semiconductor substrate, a second current associated with a temperature of the region, a third current associated with a first process parameter of the region, and a fourth current associated with a second process parameter of the region. A multiplexer of the device receives the first, second, third, and fourth currents and selects the currents one by one and periodically. A ring oscillator of the device is coupled to the multiplexer and receives the first, second, third, and fourth currents one by one and periodically, from the multiplexer. The ring oscillator oscillates at oscillation frequencies that are based on the received current from the multiplexer. The voltage, temperature, and the first and second process parameters of the region are determined based on the oscillation frequencies.Type: GrantFiled: April 3, 2023Date of Patent: July 8, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Alberto Grassi, Saurabh Surana, Ullas Singh, Namik Kocaman