Abstract: A device may include a digital-to-analog converter (DAC), including a current source, circuitry to mirror the current source, the circuitry including a transistor coupled to the current source, and a plurality of output paths, each output path of the plurality of output paths including a first switch to selectively configure a first transistor to mirror the current source, wherein each output path corresponds to a value of a respective bit of a first digital signal, and a plurality of cells, each cell of the plurality of cells including a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, wherein each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.

Abstract: A device comprising a first circuit, a second circuit, and a third circuit. The first circuit to receive, from an amplifier, a first signal having a first amount of power. The first circuit to also determine, based on the first amount of power, a range of power associated with transmission of the first signal by a transmitter. The second circuit to receive a second signal to define one or more characteristics of the second circuit. Receipt of the second signal, by the second circuit, can cause the second circuit to adjust the first signal from the first amount of power to a second amount of power. The third circuit to receive, from the second circuit, the first signal having the second amount of power, and the third circuit to provide a third signal having a voltage level to indicate a third amount of power transmitted by the transmitter.

Abstract: A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

Abstract: The disclosure describes systems and methods for downlink channel sounding in multi-access point (multi-AP) networks. The system can be configured to provide one or more sounding options. In joint sounding options, stations can measure the combined downlink channel from all the APs and can provide feedback on the composite channel. In individual sounding options, stations can measure the downlink channel from each AP separately and can provide feedback on the individual channels. In implicit sounding options, each AP can estimate the uplink channel transmitted by the stations. The uplink channel information can then be used to derive the corresponding downlink channel.

Abstract: In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

Abstract: In some implementations, the circuitry may include a circuit configured to receive a baseband signal, the baseband signal having an intermodulated non-linear distorted portion and a harmonic distorted portion. In addition, the circuitry may include a compensator coupled to the circuit, the compensator configured to generate a value to compensate for the intermodulated non-linear distorted portion without compensating for the harmonic distorted portion. The circuitry may include where the compensator is configured to output the value. The circuitry may include where the circuit is configured to adjust the baseband signal using the value. In some embodiments, the baseband signal can be baseband voltage. In some embodiments, the value can be a complex number.

Abstract: Wide-band output isolation is provided. A device includes a first output for a first radio frequency (RF) signal. A device includes a second output for a second RF signal. The device includes a first transistor having a first source/drain. The device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.

Abstract: Wide-band matching in out-of-band blocker rejection filters is provided. A device includes a first inductor. The device includes a second inductor magnetically coupled with the first inductor and with an amplifier. The device includes a notch filter electrically coupled between the first inductor and the second inductor. The amplifier can be configured to amplify a plurality of radio frequency signals. A bandwidth of the radio frequency signals can exceed 1.5 gigahertz (GHz).

Abstract: A device to receive a first signal from a driver. The device comprising a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit to provide a second signal having a first level. The second circuit to detect the first level of the first signal and to provide a third signal to control a third circuit of the device. The third circuit to provide a fourth signal, the fourth signal having a first level in response to a difference being smaller than a predetermined value, and the fourth signal having a second level in response to the difference being larger than the predetermined value. The fourth circuit to provide a fifth signal, the fifth signal having a first level based at least on the second signal, and the fifth signal having a second level based at least on the second signal and the fourth signal.

Abstract: Wide-band output isolation is provided. A device includes a first output for a first radio frequency (RF) signal. A device includes a second output for a second RF signal. The device includes a first transistor having a first source/drain. The device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.

Abstract: A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

Abstract: In some aspects, the disclosure is directed to methods and systems for reducing memory utilization and increasing efficiency during affine merge mode for versatile video coding by utilizing motion vectors stored in a motion data line buffer for a prediction unit of a second coding tree unit neighboring a first coding tree unit to derive control point motion vectors for the first coding tree unit.

Abstract: Described herein are related to a device for communication. In one aspect, the device a first circuit configured to generate a signal. In one aspect, the device includes a port. In one aspect, the device includes a set of switches. Each switch of the set of switches may be coupled in parallel between the first circuit and the port. In one aspect, the device includes a second circuit configured to enable a subset of the set of switches, according to an amplitude of the signal.

Abstract: A system includes a voltage booster circuit to receive an input voltage and provide an output voltage. A first device that is coupled to the voltage booster circuit to receive a digitized input voltage and a digitized output voltage and to determine, based on the digitized input voltage and the digitized output voltage, a first threshold level for the voltage booster circuit to operate in a pulse frequency modulation (PFM) mode. A second device that is coupled to the voltage booster circuit to receive the input voltage and the output voltage and to determine a second threshold level for the voltage booster circuit to operate in the PFM mode. A selector device that is coupled to the first device and the second device to select one of the first threshold level or the second threshold level for the voltage booster circuit.

Abstract: In some implementations, the system may include one or more processors, coupled to memory, the processor configured to set in the memory a pool of shared send queues (SSQs), each SSQ in the pool of SSQs is configured for use as a send queue (SQ) for one or more queue pairs (QPs). The one or more processors may allocate at least one of SSQs from the pool of SSQs to the QP, the SSQ set for a process having a plurality of connections to a plurality of remote processes. The one or more processors may send by the SSQ, via the plurality of connections, outgoing messages to separate remote processes of the plurality of remote processes. Also, the system may include implementations where the pool is set responsive to a first number of the QPs reaching a threshold. The system may include implementations where the pool of SSQs is pinned in the memory.

Abstract: Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.

Abstract: The technical solution is directed to ultra-high reliability (UHR) extended long-range (ELR) packet formats for enhanced long-range communications and applications. A sender can identify data to be transmitted wirelessly to a receiver according to UHR-ELR format. The sender can generate a preamble for a PPDU frame of the UHR-ELR format. The preamble can include slots for a legacy portion and for the UHR-ELR portion. The sender can include an ELR symbol in a slot the legacy portion to auto-detect that the PPDU frame is for UHR-ELR. The sender can identify a power boost for transmitting at least a L-STF or a L-LTF and transmit the PPDU frame providing the power boost to the L-STF or the L-LTF.

Abstract: A data storage controller is provided that includes: a computer-readable storage medium storing one or more sequences of instructions; and one or more processors configured to execute the one or more sequences of instructions to: receive a host write request for a logical drive corresponding to a redundant array of physical drives, wherein the redundant array of physical drives comprises a first physical drive of a first drive type and a second physical drive of a second drive type different from the first drive type, and wherein data stored on the first physical drive is mirrored on the second physical drive; generate and issue a first input-output (IO) request for the first physical drive based on the host write request and a first cache policy associated with the first drive type; and generate and issue a second IO request for the second physical drive based on the host write request and a second cache policy associated with the second drive type, wherein the first cache policy is different from the second

Abstract: A network device includes at least one port and a processor for use in a network for communicating a packet. The processor is configured to obtain a packet header for a packet and perform telemetry using postcard and/or passport approaches. The processor uses a repurposed field in the packet header to indicate telemetry is to be performed on the packet.

Abstract: A memory system includes a firmware unit and a cache module that includes a cache controller and a cache memory. The cache controller receives an I/O message that includes a local message ID (LMID) and data to be written to a logical drive (LD), stores the data in a cache segment (CS) row of the cache memory and sends an ID of the CS row to the firmware unit. The firmware unit, in response to receiving the ID of the CS row, acquires a timestamp and stores the timestamp to check against a cache flush timeout for the CS row. The firmware unit periodically checks cache flush timeout and in response to detecting the cache flush timeout, sends a flush command with the ID of the CS row to the cache controller. The cache controller, in response to receiving the flush command, flushes the first data of the CS row.