Abstract: The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.

Abstract: The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector.

Abstract: The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a magnetic memory element film stack on a substrate; depositing a selector film stack on top of the magnetic memory element film stack; etching the selector film stack with an etch mask formed thereon to remove at least a switching layer in the selector film stack not covered by the etch mask, thereby forming a selector pillar; depositing a first conforming dielectric layer over the selector pillar and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the switching layer of the selector pillar; and etching the magnetic memory element film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.

Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.

Abstract: The present invention is directed to a computer subsystem that includes a central processing unit (CPU); one or more byte-addressable memory modules having a dual in-line memory module (DIMM) form factor connected to the CPU via a first memory channel; and a master persistent memory module and one or more slave persistent memory modules having the DIMM form factor connected to the CPU via a second memory channel. The master persistent memory module and the one or more slave persistent memory modules are connected in a daisy chain configuration. The one or more slave persistent memory modules receive commands directly from the master persistent memory module.

Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.

Abstract: The present invention is directed to a magnetic tunnel junction (MTJ) memory element including a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer; a magnesium oxide layer formed adjacent to the magnetic fixed layer; and a metal layer comprising nickel and chromium formed adjacent to the magnesium oxide layer. The magnetic reference layer structure includes a first and a second magnetic reference layers with a first perpendicular enhancement layer (PEL) interposed therebetween. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction opposite to the first invariable magnetization direction.

Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an oxide layer formed adjacent to the magnetic free layer structure; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the oxide layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.

Abstract: The present invention is directed to an MTJ memory element, which comprises a magnetic fixed layer structure formed on top of a seed layer structure that includes a first seed layer and a second seed layer. The first seed layer includes one or more layers of nickel interleaved with one or more layers of a transition metal, which may be tantalum, titanium, or vanadium. The second seed layer is made of an alloy or compound comprising nickel and another transition metal, which may be chromium, tantalum, or titanium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first type material interleaved with layers of a second type material with at least one of the first and second type materials being magnetic. The first and second type materials may be cobalt and nickel, respectively.

Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.

Abstract: A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.

Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer comprising cobalt, iron, and boron formed adjacent to the insulating tunnel junction layer; a second magnetic reference layer comprising cobalt separated from the first magnetic reference layer by a molybdenum layer; an iridium layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the iridium layer. The magnetic free layer structure includes a first and a second magnetic free layers with a perpendicular enhancement layer interposed therebetween. The first and second magnetic reference layers have a first invariable magnetization direction perpendicular to layer planes thereof.

Abstract: The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.

Abstract: The present invention is directed to an MTJ memory element, which includes a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; a tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure formed adjacent to the tunnel junction layer and having a first invariable magnetization direction perpendicular to a layer plane thereof; an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure; and a magnetic fixed layer structure formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction that is perpendicular to a layer plane thereof and is opposite to the first invariable magnetization direction. The magnetic fixed layer structure includes multiple stacks of a trilayer unit structure, which includes three layers of different materials with at least one of the three layers of different materials being magnetic.

Abstract: The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.

Abstract: A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

Abstract: The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.

Abstract: The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.