Abstract: A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.

Abstract: The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

Abstract: The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

Abstract: An overhead processor for data transmission in digital communications, where a state machine, including a logic element and a flip-flop, is able to process a “previous” data state and a “next” data state simultaneously by storing the previous state in an external elastic storage element until the next state arrives along the datapath.

Abstract: The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.

Abstract: The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilising a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip architecture samples the incoming data signal in response to a clocking signal input from the physical delay line; the physical delay line responds to commands from the state machine to increment the delay of the physical delay line to produce samples which describe the incoming data signal and delineate its data valid window.

Abstract: The present invention discloses an apparatus to implement a m=n Non-Blocking Minimal Spanning Switch, where n=the total number of data input signals and m=the total number of data output signals and m=the number of crossbar connections in each switch. Data is input to the switch as a plurality of frames, whereby each crossbar connection contains a framer which detects framing patterns in the data. Skewed data is re-aligned and buffered so that the data output by each crossbar connection is equal and identical, thus any crossbar connection may be used to ensure a connection, eliminating the possibility of data interrupts.

Abstract: The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).

Abstract: The present invention discloses a method of detecting and correcting skew across a plurality of transmitting lanes. Through the use of an N framer system, including a frame start signal and a frame synchronization signal, skew can be detected and corrected by writing data from a plurality of framers into offsetting bit locations of a plurality of buffers. The present invention also provides a method of transmitting data in a multiple lane distribution (MLD) transmission system.

Abstract: A method for performing serial functions in parallel, where a datapath is divided into several independent stages, or pipeline stages, so that logical functions can be implemented in each pipeline stage concurrently. In an illustrative embodiment of the invention, a pipelined logic tree is described. This method allows for n-bits to be input to the system and n-bits to output from the system concurrently.

Abstract: An apparatus for determining the amount of skew to be injected into a high-speed data communications system of including a plurality of lanes having a data bus per lane, relative to a reference lane, for system skew compensation. By knowing the relative amount of skew that each lane requires for alignment, an appropriate amount of skew can be injected on each lane to provide alignment and thus compliancy with the SFI-5 and SxI-5 standards, in terms of data skew specifications. The relative skew amounts for each transmitting lane are determined using a methodology involving internal loopback and characteristics from a connected communications element to the chip receive path.

Abstract: The present invention discloses a method of mapping Optical Payload Unit (OPU) k (k=1, 2, 3 or any positive integer) Ethernet signals (E) into Optical Transport Network (OTN) frames for 10 Gigabit Ethernet (10 GbE) Local Area Network Physical Layer (LAN PHY), wherein OPUk Overhead (OH) is altered by the relocation of Justification Control (JC) bytes, from the standardized ITU-T G.709 locations, into the novel locations of rows 1-3 of column 15. This allows for rows 1-4 of column 16 to be available for any type of Justification Overhead (JOH), such as four Negative Justification Opportunity (NJO) byte locations. Four NJO byte locations, combined with four Positive Justification Opportunity (PJO) byte locations in rows 1-4 of column 17, provides for up to nine justification state choices to be determined by the JC bytes.

Abstract: The present invention discloses a method of accessing stored information in multi-framed data transmissions, comprising at least one control interface and at least one elastic store, wherein the control interface accesses the elastic store through a mailbox communications method.

Abstract: An apparatus for determining the amount of skew injected into a high-speed data communications system, including a plurality of lanes having a data bus per lane, relative to a reference lane, for system skew compensation. By knowing the relative amount of skew that each lane requires for alignment, an appropriate amount of skew is then injected on each lane to provide alignment and thus compliancy with the SFI-5 and SxI-5 standards, in terms of data skew specifications. The relative skew amounts for each transmitting lane are determined using dual loopback methods.

Abstract: An apparatus for determining the amount of skew to be injected for system skew compensation in a high-speed data communications system including a plurality of lanes with a data bus per lane. Such skew compensation is necessary due to inherent system skew. By iterating through the possible intervals within the maximum expected skew search space, the correct combination of search space intervals for all lanes can be determined to provide alignment and thus compliancy with relevant standards, such as the SFI-5 and SxI-5 standards, in terms of data skew specifications.

Abstract: The present invention discloses an overhead processor for data transmission in digital communications. First, incoming data is transmitted along a datapath. If the incoming data forms one group of data, said group of data is transmitted along the datapath, into an elastic store and then is transmitted into one or more flip-flop(s); if there are two or more groups of incoming data, arriving separately, the initial group(s) of received data can optionally be held in an elastic store until the arrival of additional group(s) of data, and upon the arrival of said additional group(s) of data, all of the received data are combined and then transmitted into said flip-flop(s). The data is then transmitted from said flip-flop(s) to a logic element, which uses the received data context to determine the new data context of any imminent incoming data. The logic element transmits this new data context to a second flip-flop, which transmits the new data context values into an elastic store.

Abstract: A present invention discloses a method for performing forward error correction (FEC) in long-haul submarine transmission systems. Data is encoded at a transmitter by serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes. The invention encodes a stream of data employing a plurality of serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes, arranging said data into a frame of parallel data blocks (the outer frame) with redundancy bits appended by a BCH(3896, 3824) code; the outer frame is then interleaved to produce a frame of serial data blocks (the intermediate frame); and the final frame (the inner frame) is produced by appending the redundancy bits of the BCH(2040, 1952) code to the intermediate frame. The data, once encoded, is transmitted across a datapath and decoded at the receiver.

Abstract: This algorithm and apparatus provides the ability to determine the amount of skew that should be injected into a high-speed data communications system consisting of a plurality of lanes comprising a data bus on a per lane basis, relative to a reference lane, for the purpose of compensating for inherent system skew. By knowing the relative amount of skew that each lane requires for alignment, an appropriate amount of skew can then be injected on each lane to provide alignment and thus compliancy with relevant standards, such as the Sxl-5 standard, in terms of data skew specifications. These relative skew amounts for each transmitting lane are determined using a methodology involving internal loopback and characteristics from the connected communications element to the chip receive path.