Abstract: A layout versus schematic (LVS) comparison tool performs layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.

Abstract: A design rule checking (DRC) tool performs DRC operations by determining a match between one of a plurality of waiver layout patterns and a first portion of an integrated circuit layout containing a suspected violation of a first design rule. This operation is preferably performed automatically during a comprehensive DRC operation on the entire integrated circuit layout. Each violation of a design rule within an integrated circuit layout is preferably treated initially as a “suspected” violation prior to an operation to compare one or more different waiver layout patterns to the portion of the integrated circuit containing the “suspected” violation. A failure to identify a match with any of the waiver layout patterns operates to convert the “suspected” violation into a “confirmed” violation.

Abstract: A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0.

Abstract: Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets.

Abstract: The Model Editor (106) makes simulation modeling easier and more intuitive by extracting essential information and presenting it to the user, and by providing tools to investigate simulation and model robustness, in an interactive, graphical environment. The Model Editor (106) includes a Newton step manager as an interactive, graphical tool. During simulation of a model, the Newton step manager captures matrix norms. Any indications of Newton limiting are also captured. The matrix norms are plotted as a function of iteration count, and the iterations at which Newton limiting were encountered are identified. Newton step manager can also be run automatically using a functional dependency analysis.