Abstract: A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance.

Abstract: A T-shaped electrode is formed on a semiconductor substrate by first forming a dielectric film on the substrate. A first layer of photoresist is applied on the upper surface of the dielectric film, and a second layer of photoresist is applied over the first layer of photoresist. The first and second layers of photoresist have different optical properties, requiring different wavelengths of ultraviolet for exposure before developing. Portions of the first and second photoresist layers and the dielectric film are selectively removed by photolithographic techniques with one masking step for forming an opening to the substrate. The first and second photoresist layers adjacent to the opening are ion etched to expose the upper surface of the dielectric film adjacent to the opening. A portion of the first photoresist layer adjacent to the opening is removed to undercut the second photoresist layer. Metal is deposited in the opening and on the exposed upper surface of the dielectric film to form a T-shaped electrode.

Abstract: A thin film printed circuit inductive element exhibiting low Q wherein a conductive spiral is deposited on an insulating substrate and resistive links are connected between adjacent turns of the spiral. Inherent resonance is thereby damped out.

Abstract: A method for thinning a Gallium Arsenide (GaAs) layer on the backside of a wafer substrate is provided. The method involves spraying an etchant solution including NH.sub.4 OH and H.sub.2 O.sub.2, preferably in a 1:4 ratio, onto the GaAs layer as the wafer is rotated at approximately 2000 rpm. The etchant is sprayed through a plurality of spray nozzles. The process is capable of thinning a GaAs layer by about 500 .mu.m in approximately 14 to 18 minutes, depending on the etchant temperature and composition.

Abstract: A semiconductor chip header includes an electrically insulative base member having a centrally located aperture and electrically separate metalizations. Where the semiconductor chip is a transistor, two metalizations originate on the top surface of the base member on opposing sides of the aperture, wrap around the outer edges and terminate on the bottom surface of the base member. These metalizations' termination areas are for connecting two ribbon leads (e.g. via eutectic bonding) during final assembly and packaging of a transistor. A third metalization is deposited upon a portion of the bottom surface of the base member, and surrounds the aperture. The third metalization is for connecting a third ribbon lead covering the aperture during final assembly. The aperture allows a transistor chip to be positioned therein during final assembly with its bottom chip surface (e.g. substrate) bonded directly to the third ribbon lead.

Abstract: A synchronous, interleaved, time-division M:1 multiplexor. Following an input stage of parallel synchronous latches for latching M incoming parallel data bits (where M is an integer power of two equal to or greater than four) is an intermediate stage of parallel synchronous latches. The intermediate latches are clocked with selected phases of an M-phase clock having M equally-spaced phases of a clock signal having a frequency of B/M (where B is the outgoing bit rate) to latch each bit at a time at least 2/B (i.e., two outgoing bit periods) after such bit is received from its respective input latch. A first stage of 2:1 multiplexors, following the intermediate latches and used to begin multiplexing the latched bits, are clocked with selected phases of the M-phase clock to begin multiplexing each bit at a time at least 1/B (i.e., one outgoing bit period) after such bit is received from its respective intermediate latch.

Abstract: A 180 degree ultraminiature phase shifter. Only two switching devices and very few passive circuit elements are required, thus allowing an extremely small and low loss device to be fabricated. When power is applied to switching devices, a low pass pi section low pass filter is realized which provides +90 degrees of phase shift. When power is absent from the switching devices, a T section high pass filter is realized which provides -90 degrees of phase shift.

Abstract: A broadband YIG-tuned oscillator is disclosed that has both series and parallel feedback provided by a YIG sphere. The oscillator includes a transistor capable of driving a load coupled to a first port of the transistor, a reactive feedback element coupled to a second port of the transistor, a YIG resonator, and coupling means for coupling the YIG resonator to both a third port of the transistor and to the first port of the transistor.

Abstract: Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.

Abstract: Adjacent microwave circuit modules are coaxially connected by means of insulating plugs, in which through-pins are embedded, recessed mounted in bores in the opposed walls of a pair of modules and an inter-connector made of an insulating material and containing sockets for mating with the through-pins, the inter-connector being dimensioned such that it can be inserted half way into each of the bores.

Abstract: A balun section formed of a pair of transmission lines connected between separate pairs of corresponding input and output terminals with a pair of capacitors connected in series between the output terminals and another transmission line connected in series with a resistor between the circuit ground and the interconnection between the pair of capacitors. A multisection balun is constructed from a plurality of such balun sections connected in cascade. In one embodiment, the outputs of a pair of multisection baluns are supplied to a circuit such as a mixer or the like.

Abstract: A broadband RF amplifier with high efficiency and high reverse isolation having a common emitter stage connected in a cascode configuration to a common base stage, said cascode driving the common base stage in a push-pull operation with a common collector stage.

Abstract: A branch line coupler is disclosed. The device is comprised of multiple ports and branch lines, every two such lines being connected in a junction point. Each branch line has a width which is narrow at each end and increases in a curvilinear manner toward the middle. By virtue of the width design, the device performs the same functions as a conventional coupler, but for much higher frequencies.

Abstract: A thin film printed circuit inductive element exhibiting low Q wherein a conductive spiral is deposited on an insulating substrate and resistive links are connected between adjacent turns of the spiral. Inherent resonance is thereby damped out.

Abstract: A circuit for biasing a field effect transistor using a current source to provide a constant current which can be shared between amplifier stages by connecting it to the drain of a first stage and the source of a second stage.

Abstract: A conductive device for protecting and securing electrical circuit substrates during manufacture and shipment which includes a plurality of spring driven pin slides anchored on a common support member, each slide securing a substrate against a corresponding substrate stop.

Abstract: A thin-film, lumped element filter utilizing spiral inductors and capacitive pi networks is disclosed. The filter is fabricated from a planar dielectric substrate having a ground plane on one side thereof and two thin-film metal layers and an insulation layer disposed therebetween on the opposite side of the dielectric substrate. The metal and insulation layers are configured to form one or more capacitive pi networks and spiral inductors, which are electrically interconnected to form the filter.

Abstract: A frequency divider circuit for use in a programmable frequency synthesizer is disclosed and comprises a dual modulus prescaler, a fixed divider, a programmable counter, and a programmable fractional divider. The feedback signal is generated directly by the dual modulus prescaler, rather than by circuitry downstream from the dual modulus prescaler.

Abstract: A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;(c) forming via-holes through said wafer;(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.

Abstract: A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.