Patents Assigned to AVARY HOLDING (SHENZHEN) CO., LTD.
  • Patent number: 12191056
    Abstract: A buried thermistor includes a lower substrate, an upper substrate, and a number of thermistor stacks. Each thermistor stack includes two resistor subjects. Each resistor subject includes a base layer, a medium layer, a metal layer, a resistor layer, a nanometal layer, and a conductive layer. Applicable material of the resistor layer becomes more diverse by disposing the number of thermistor stacks, and the buried thermistor shows variable thermal sensitivity.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 7, 2025
    Assignees: HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO., LTD., AVARY HOLDING (SHENZHEN) CO., LTD., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Jian Wang, Jun Dai, Xiao-Juan Zhang
  • Patent number: 12120812
    Abstract: A circuit board includes a dielectric substrate, a signal line and a pair of ground wires. The dielectric substrate includes a base and an elevated platform protruding from an upper surface of the base. The signal line is conformally disposed on the dielectric substrate and includes a first segment disposed on an upper surface of the elevated platform, a second segment extending on the upper surface of the base, and a third segment disposed on a sidewall of the elevated platform and connecting the first segment and the second segment. The pair of ground wires are disposed on the dielectric substrate and are spaced apart from the signal line. A projection of the second segment of the signal line on the upper surface of the base partly overlaps projections of the pair of ground wires on the upper surface of the base.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 15, 2024
    Assignees: HongQiSheng Precision Electronics (QinHuangdao) Co., Ltd, Avary Holding (Shenzhen) Co., Ltd., Garuda Technology Co., Ltd.
    Inventors: Hao-Yi Wei, Childe Zhu, Yan-Lu Li
  • Patent number: 12108533
    Abstract: A method for manufacturing a circuit board includes disposing an electronic component in a recess formed in a first circuit substrate, and bonding a second circuit substrate to the first circuit substrate to form a third circuit substrate with the electronic component embedded. The method includes forming an opening in the third circuit substrate to expose the electronic component and an inner surface of the third circuit substrate. The method includes disposing an insulation case in the opening. The insulation case has a first segment directly contacting the electronic component, a second segment facing the inner surface, an inner wall between the first and second segments, a first chamber surrounded by the first segment and the inner wall, and a second chamber surrounded by the second segment and the inner wall. The method includes adding a heat-exchanging fluid into the first chamber.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: October 1, 2024
    Assignees: AVARY HOLDING (SHENZHEN) CO., LTD., QINGDING PRECISION ELECTRONICS (HUAI'AN) CO., LTD., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Zhi Guo, Chen Xiong, Po-Yuan Chen
  • Patent number: 12028967
    Abstract: A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 ?m. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: July 2, 2024
    Assignees: Avary Holding(Shenzhen)Co., Ltd., HongQiSheng Precision Electronics(QinHuangdao)Co., Ltd., Garuda Technology Co., Ltd.
    Inventors: Mao-Feng Hsu, Zhi-Hong Yang
  • Patent number: 11792914
    Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and first shielding columns. The core layer includes an accommodating space, and the accommodating space has an inner side wall. The first shielding ring wall is disposed in the accommodating space and covers the inner side wall, in which the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding columns are disposed in the first insulating layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 17, 2023
    Assignees: AVARY HOLDING (SHENZHEN) CO., LTD., HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO., LTD., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Zhi-Hong Yang, Mao-Feng Hsu
  • Patent number: 11696391
    Abstract: A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 ?m. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: July 4, 2023
    Assignees: AVARY HOLDING (SHENZHEN) CO., LTD., HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO., LTD., GARUDA TECHNOLOGY CO., LTD
    Inventors: Mao-Feng Hsu, Zhi-Hong Yang