Abstract: The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks.

Abstract: The present invention provides for adaptive filters that have improved computational and memory bandwidth proprieties. When applied to telecommunication applications, the present invention additionally provides for improved methods and systems of canceling echoes. In one embodiment of the adaptive filter of the present invention, a filter, preferably an adaptive finite impulse response (FIR) filter, of an appropriate length, N, is chosen. Once the filter is chosen, convergence is achieved and the filter is converted to an infinite impulse response (IIR) filter. In the course of operation, data is received from an input source and used to adapt the zeroes of the IIR filter using the least means square (LMS) approach, keeping the poles fixed. The adaptation process generates a set of converged filter coefficients that are then applied to the input signal to create a modified signal used to filter the data.