Patents Assigned to Averant, Inc.
  • Circuit-level memory and combinational block modeling
    Patent number: 7516060
    Abstract: A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: April 7, 2009
    Assignee: Averant, Inc.
    Inventor: Adrian J. Isles
  • Circuit-level memory and combinational block modeling
    Patent number: 6968305
    Abstract: A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: November 22, 2005
    Assignee: Averant, Inc.
    Inventor: Adrian J. Isles
  • Determining verification coverage using circuit properties
    Patent number: 6594804
    Abstract: A system is disclosed to provide static coverage analysis. The system receives at least two inputs including a hardware description and a set of properties. Using the methods of the present invention, the system determines what portions of the design can be verified using the set of properties. In one embodiment, the invention includes three levels of analysis. Each level provides a different tradeoff between level of accuracy and speed.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: July 15, 2003
    Assignee: Averant, Inc.
    Inventor: Ramin Hojati