Patents Assigned to AVERATEK CORPORATION
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Patent number: 12213258Abstract: Devices and methods for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.Type: GrantFiled: October 16, 2019Date of Patent: January 28, 2025Assignee: Averatek CorporationInventors: Haris Basit, Michael Riley Vinson, Shinichi Iketani
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Patent number: 12063748Abstract: Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 ?m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 ?m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.Type: GrantFiled: February 12, 2021Date of Patent: August 13, 2024Assignee: Averatek CorporationInventors: Shinichi Iketani, Sunity K Sharma, Gary Lawrence Borges, Michael Riley Vinson
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Patent number: 11877404Abstract: Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 ?m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 ?m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.Type: GrantFiled: March 22, 2021Date of Patent: January 16, 2024Assignee: Averatek CorporationInventor: Shinichi Iketani
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Patent number: 11716819Abstract: The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.Type: GrantFiled: June 21, 2019Date of Patent: August 1, 2023Assignee: Averatek CorporationInventors: Michael Riley Vinson, Shinichi Iketani
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Patent number: 11597042Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: GrantFiled: November 20, 2018Date of Patent: March 7, 2023Assignee: Averatek CorporationInventors: Michael Riley Vinson, Calvin Chen, Divyakant P Kadiwala, Sunity K Sharma
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Patent number: 11549184Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.Type: GrantFiled: October 1, 2021Date of Patent: January 10, 2023Assignee: Averatek CorporationInventors: Sunity K. Sharma, Shinichi Iketani
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Patent number: 11142825Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.Type: GrantFiled: February 3, 2020Date of Patent: October 12, 2021Assignee: AVERATEK CORPORATIONInventors: Sunity K. Sharma, Shinichi Iketani
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Patent number: 11076492Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.Type: GrantFiled: December 17, 2019Date of Patent: July 27, 2021Assignee: Averatek CorporationInventors: Shinichi Iketani, Michael Riley Vinson, Haris Basit
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Patent number: 10034386Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: GrantFiled: June 23, 2017Date of Patent: July 24, 2018Assignee: AVERATEK CORPORATIONInventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Patent number: 9699914Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: GrantFiled: October 20, 2015Date of Patent: July 4, 2017Assignee: AVERATEK CORPORATIONInventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma