Patents Assigned to Avery Design Systems, Inc.
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Patent number: 11321507Abstract: A computer executable system that runs symbolic simulation with formal X-analysis along with logic simulation to determine if Xs produced in logic simulation are real or not. Simulated values in logic simulation shown to be incorrect are rectified using formal analysis results to produce X-accurate simulation results that match real hardware.Type: GrantFiled: April 13, 2020Date of Patent: May 3, 2022Assignee: Avery Design Systems, Inc.Inventor: Kai-Hui Chang
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Patent number: 11263376Abstract: A computer executable tool fixes gate-level logic simulation when unknowns (Xs) exist in nested clock gater chains to improve simulation accuracy. Due to X-pessimism in logic simulation, false Xs are generated when simulating nested clock gaters, producing incorrect simulation results. The tool analyzes the fan-in cones along a nested clock gater chain to find such false Xs. Furthermore, it generates auxiliary code to be used with logic simulation to eliminate such false Xs. Gate-level simulation can then be repaired to produce correct results for nested clock gaters.Type: GrantFiled: June 23, 2020Date of Patent: March 1, 2022Assignee: Avery Design Systems, Inc.Inventor: Kai-Hui Chang
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Patent number: 10852354Abstract: A computer executable tool analyzes Boolean logic in a gate-level netlist with simulated values and efficiently determines whether a subset of the netlist produces real Xs or not. If whether the netlist produces real Xs or not cannot be quickly determined, further formal analysis needs to be performed, and this step can be time-consuming. By quickly determining whether real Xs are produced, the use of time-consuming formal methods can be reduced, thus reducing X-pessimism analysis time.Type: GrantFiled: November 15, 2019Date of Patent: December 1, 2020Assignee: Avery Design Systems, Inc.Inventor: Kai-Hui Chang
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Patent number: 10794954Abstract: A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.Type: GrantFiled: August 30, 2019Date of Patent: October 6, 2020Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Hong-zu Chou, Yueh-Shiuan Tsai
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Patent number: 10740521Abstract: A computer executable system and method analyzes a circuit design to extract a small set of signals for value collection using an emulator system. The collected signals are for specific purpose checkers such as assertions or interactive testbenches that are hard to emulate. A synthesizable monitor block is generated and added to the emulation environment to collect the signal value changes during emulation. The collected values are then used in localized logic simulation to perform the tasks that the original checkers intent to accomplish. This system leverages fast emulation speed and flexible logic simulation capabilities to perform the intended checker tasks much faster than using logic simulation alone.Type: GrantFiled: March 26, 2019Date of Patent: August 11, 2020Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Christopher S. Browy
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Patent number: 10726180Abstract: A computer executable processing component analyzes unknown (X) propagation from uninitialized latches in gate-level simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues. A computer executable processing component analyzes unknown (X) propagation from sequential cells in gate-level logic simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues.Type: GrantFiled: February 20, 2019Date of Patent: July 28, 2020Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Andrew Stein, Hong-zu Chou, Christopher S. Browy, Chi-Lai Huang
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Patent number: 10666255Abstract: A computer executable tool analyzes Boolean logic in a gate-level netlist responsible for generating false Xs due to X-pessimism in logic simulation to produce a compact fix that corrects the X-pessimism problem. The fix restores logic simulation value from X to hardware-accurate non-X value and solves X-pessimism issues in logic simulation.Type: GrantFiled: October 30, 2017Date of Patent: May 26, 2020Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Hong-zu Chou
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Patent number: 9058452Abstract: A computer executable tool analyzes unknowns (Xs) in gate-level simulation and traces their sources to determine if the Xs are generated due to X-pessimism. For Xs generated due to X-pessimism, fixes are generated to correct simulation results. Corrected simulation results match real hardware behavior and greatly reduce the analysis effort of engineers.Type: GrantFiled: February 28, 2014Date of Patent: June 16, 2015Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Yen-Ting Liu, Christopher S. Browy, Chi-Lai Huang
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Patent number: 8938705Abstract: A retention synthesis application provides a means of analyzing a circuit design, functional test sequences, and the associated power specification to identify registers that do not need retention when a block is powered down. Reducing the number of retention registers reduces power consumption and chip area. The retention synthesis application is based, at least in part, upon symbolic simulation. In symbolic simulation, a symbol is used to represent a value that can be either 0 or 1 and the propagation of symbols is traced through the simulation.Type: GrantFiled: June 1, 2014Date of Patent: January 20, 2015Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Yen-Ting Liu, Christopher S. Browy, Chi-Lai Huang
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Patent number: 8402405Abstract: This invention provides a system and method for correcting gate-level simulation commences by identifying unknown values (Xs) that are falsely generated during the simulation of a given trace for a design netlist. Then, a sub-circuit of the design netlist is determined for each false X that has inputs of real Xs and an output of a false X. Finally, simulation correction code is generated based on the sub-circuit to eliminate false Xs in simulation of the design netlist. The original design netlist can then be resimulated with the simulation repair code to eliminate false Xs. This allows gate-level simulation to produce correct results.Type: GrantFiled: May 22, 2012Date of Patent: March 19, 2013Assignee: Avery Design Systems, Inc.Inventors: Kai-Hui Chang, Yen-Ting Liu, Christopher S. Browy, Chilai Huang