Abstract: An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links.

Abstract: A router coupled to a plurality of external links transporting data packets to and from the router. Embodiments of the router including a plurality of fabric routers interconnected by fabric links forming or capable of forming a Gamma graph interconnection network. One or more external links are coupled to each fabric router allowing the routing of packets between external links by traversing one or more hops across the fabric links. The Gamma graph interconnection network of the router providing for high port counts and increased bandwidth availability. Furthermore, the use of industry standard buses, such as Infiniband buses, allow for the interconnection of multiple heterogeneous application specific modules to interface and communicate with one another.

Abstract: A network is disclosed for interconnecting devices external to the network. Embodiments of the network include a plurality of switching nodes interconnected by links forming or capable of forming a Gamma graph interconnection network. Devices are coupled to the network via a plurality of ports. Furthermore, the network includes a plurality of Infiniband buses with each switching node coupled to at least one of the buses. Each Infiniband bus is capable of supporting a configurable number of ports such that the bandwidth of a port is inversely proportional to the number of ports configured per bus. The Gamma graph interconnection network of the router providing for high port counts and increased bandwidth availability. Furthermore, the use of industry standard buses, such as Infiniband buses, allow for the interconnection of multiple heterogeneous application specific modules to interface and communicate with one another.

Abstract: In scheduling a packet, latency requirements of the packet is determined. The packet is then scheduled according to its latency requirements. Queues may be assigned latency ranges and packets are assigned to the queues according to those ranges. Within ranges, queues of different priorities may be provided.

Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.

Abstract: An interconnection network, particularly a Gamma graph network, comprising a number of interconnected routers implementing source based and egress based virtual networks in order to prevent tree saturation and deadlock while routing packets. The interconnection network can be used as a fabric within a multi-application switch router, for example. Packets traverse the fabric from any packet source to any packet destination by traversing a source based virtual network associated with a packet source and then by traversing an egress based virtual network associated with a packet destination. By partitioning the fabric into source based virtual networks and egress based virtual networks, the number of control structures required to manage them are reduced as compared with destination based virtual network architectures.

Abstract: Queuing operations are separated into distinct logical blocks despite the need to share information. Preparatory operations such as queue status fetching, correctness check and random early drop operation may be performed in one or more logical blocks and the completion of the queuing operation, either enqueuing, dequeuing or both, may be performed in another logical block. The operations processed in the first logical block may pass information to the operations processed in the second logical block to improve sharing of information.

Abstract: Sort elements, such as queues processed in a network processor, are provided with relative priorities relative to each other. A set of relative priorities is used to specify priority order of the sort elements. The priority order may be specified by addressing code in a jump table. Duplicate code in the jump table having multiple entrance points allows for reduction of the size of the jump table. The relative priorities may be applied to a lookup table, hash or other function in order to address the jump table.

Abstract: An optical data stream is converted to electrical signals which are applied to a time-slot interchanger. The time-slot interchanger recorders the packets or cells of the data stream to correspond to the schedule of an optical switch. The time-slot interchanger may contain a plurality of FIFOs implemented as circular buffers in a single dual port memory. The switch schedule may be determined by the average load between inputs and outputs and may be determined by the number of packets or cells queued from each input or each output in the time-slot interchangers.

Abstract: Paths for packets traveling through a distributed network fabric are chosen using information local to the source of packets. The system allows resequencing of packets at their destination and detecting out-of-order and missing packets.

Abstract: Network traffic is sent via alternate paths in cases of network link or node failure. An alternate node responds to U-Turn traffic from a primary neighbor to select a further alternate. An algorithm for determining the alternate paths is provided to select loop-free neighbors.

Abstract: Network traffic is sent via alternate paths in cases of network link or node failure. An alternate node responds to U-Turn traffic from a primary neighbor to select a further alternate. An algorithm for determining the alternate paths is provided to select loop-free neighbors.

Abstract: In a fabric router, flits are stored on chip in a first set of rapidly accessible flit buffers, and overflow from the first set of flit buffers is stored in a second set of off-chip flit buffers that are accessed more slowly than the first set. The flit buffers may include a buffer pool accessed through a pointer array or a set associative cache. Flow control between network nodes stops the arrival of new flits while transferring flits between the first set of buffers and the second set of buffers.

Abstract: A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the data packets. The router further includes control circuitry, coupled with the input and output physical channels and the data buffers, for generating virtual channel assignments that assign virtual channels to the data packets, and generating physical channel assignments that assign the output physical channels to the virtual channels. Each of the assignments is generated in response to queued arrival and credit events. The portions of the data packets are forwarded from the data buffers to the output physical channels according to the generate virtual and physical channel assignments.

Abstract: A system and method for fault tolerant data communication. Embodiments of the invention may be applied to a variety of applications, including routers that exchange routing table updates within a network environment. A primary process engages in a communication with a remote process, which includes the transfer of content and communication state. The primary process stores the content and communication state into a data store. In the event the primary process fails, the communication with the remote process is transferred to a backup process which mirrors the primary process by retrieving the content and the communication state from the data store. The backup process, thus, continues the communication with the remote process using the communication state retrieved from the data store.

Abstract: The required length of a route descriptor in a source routing system is obtained by inserting an implied exit field, use of run-length encoding, and use of variable-length encoding. In the variable-length encoding, codes having lesser bits are reserved for preferred directions. Preferred direction may be encoded in the routing header, and it may be implied by the arrival port.

Abstract: A fabric of modules includes a plurality of physically offset adjacent modules and first dimension links which, in at least one linear array of modules, connect single offset modules in a ring. The fabric also includes second dimension links which connect the modules of each linear array in at least one ring with substantially all links between modules in each array being double offset links bypassing a single module, and third dimension links which connect modules of each linear array in at least one ring with substantially all links between modules in each array being triple offset links bypassing two modules.

Abstract: A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the data packets. The router further includes control circuitry, coupled with the input and output physical channels and the data buffers, for generating virtual channel assignments that assign virtual channels to the data packets, and generating physical channel assignments that assign the output physical channels to the virtual channels. Each of the assignments is generated in response to queued arrival and credit events. The portions of the data packets are forwarded from the data buffers to the output physical channels according to the generate virtual and physical channel assignments.

Abstract: Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a single cycle which includes nodes on opposite sides of lower dimension tori. The cycles in adjacent backplanes hop different numbers of nodes.

Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.