Abstract: An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.

Abstract: A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: An electronic circuit comprising a driver and a main transistor are provided. The driver may include a bias voltage generator, a supplementary transistor, and an output driver. The bias voltage generator may be configured to receive a voltage input and generate a biased voltage output based on the voltage input. The supplementary transistor may have a gate coupled to the biased voltage output of the bias voltage generator, and a source of the supplementary transistor providing a current to the bias voltage generator. The output driver may be configured to receive the biased voltage output from the bias voltage generator and the voltage input, receive the voltage input, and output a drive voltage. The main transistor of the electronic circuit may have a gate, a coupled to the drive voltage, and a drain coupled to a drain of the supplementary transistor.

Abstract: A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Abstract: An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

Abstract: An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.

Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.

Abstract: An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

Abstract: An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe.

Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.

Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.

Abstract: A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract: A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer.

Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.