Abstract: A process of acquiring, transmitting and reconstructing data signals is disclosed. The process includes monitoring a timing reference signal produced by a timing reference and receiving an input data signals on input/output modules. The input data signals are sampled using one of an external sample clock and an internal sample clock. The process further includes recording an input rate, based on a number of samples received during an interval, a duration count, based on the number of cycles of the timing reference signal received between the first sample and the last sample in the sample interval, and a delay count, based on a number of cycles of the timing reference signal received between a start of the interval and a first sample clock cycle of the one of the external sample clock or the internal sample clock. Data packets are created, based on sampled input data and the measured input rate, the delay count for each interval.

Abstract: A process of acquiring, transmitting and reconstructing data signals is disclosed. The process includes monitoring a timing reference signal produced by a timing reference and receiving an input data signals on input/output modules. The input data signals are sampled using one of an external sample clock and an internal sample clock. The process further includes recording an input rate, based on a number of samples received during an interval, a duration count, based on the number of cycles of the timing reference signal received between the first sample and the last sample in the sample interval, and a delay count, based on a number of cycles of the timing reference signal received between a start of the interval and a first sample clock cycle of the one of the external sample clock or the internal sample clock. Data packets are created, based on sampled input data and the measured input rate, the delay count for each interval.