Abstract: An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases.

Abstract: A system and method of implementing interworking function (IWF) between frame relay and IP protocols and networks. The interworking function provides mapping and encapsulation functions necessary to ensure service provided to networks/protocols is unchanged. A frame relay service specific convergence sublayer (FR-SSCS) translates between the Q.922 and UDP/IP sublayer.

Abstract: A system and method of implementing interworking function (IWF) between ATM and IP protocols and networks. The interworking function provides mapping and encapsulation functions necessary to ensure service provided to networks/protocols is unchanged. An ATM service specific convergence sublayer (ATM-SSCS) translates between the ATM layer and RTP/UDP/IP sublayer.

Abstract: A system for a high capacity computer-based communications device is described. The system has an enhance backplane supporting a plurality of busses working independently of each other and each utilized for a different data type. The backplane supports a cPCI bus, a H.110 bus, and a StarLan bus. The system provides for increasing the capacity of the cPCI bus through bridging between two cPCI segments. A first serializer, operatively connected to the first cPCI segment, is used to receive data from a first PCI bus, serializes the data, and transfers the serial data stream to a second serializer which is operatively coupled to the second bus. The second serializer de-serializes the transferred data and transfers it to the second PCI bus. The backplane is utilized with a router and I/O modules to provide a device which combines traditional IP routing capabilities with a gateway for non-IP traffic to the IP network.

Abstract: Alternative structures and backplanes are designed so as to provide for telecom/datacom equipment conforming to either the ETSI standard or NEBS standard with minimum engineering efforts and with minimum changes in the basic parts of the products. ETSI chassis has an upper enclosure region for housing interface modules of the system and a lower enclosure region for housing system modules of the system. When assembled, a backplane is disposed along a common back wall of both enclosures. A portion of the backplane extends into the upper enclosure region from the lower enclosure region and includes connectors for receiving connectors of the interface modules. The portion of the backplane located in the lower enclosure region includes connectors for receiving connectors of the system modules.