Abstract: Methods and systems for low etch pit density gallium arsenide crystals with boron dopant may include a gallium arsenide single crystal wafer having boron as a dopant, an etch pit density of less than 500 cm?2, and optical absorption of 6 cm?1 or less at 940 nm. The wafer may have an etch pit density of less than 200 cm?2. The wafer may have a diameter of 6 inches or greater. The wafer may have a boron concentration between 1×1019 cm?3 and 2×1019 cm?3. The wafer may have a thickness of 300 ?m or greater. Optoelectronic devices may be formed on a first surface of the wafer, which may be diced into a plurality of die and optical signals from an optoelectronic device on one side of one of the die may be communicated out a second side of the die opposite to the one side.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm?2 or less, or 100 cm?2 or less, or 10 cm?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm?2 or less, or 100 cm?2 or less, or 10 cm?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Abstract: Systems and methods are disclosed for crystal growth including features of reducing micropit cavity density in grown germanium crystals. In one exemplary implementation, there is provided a method of inserting an ampoule with raw material into a furnace having a heating source, growing a crystal using a vertical growth process wherein movement of a crystallizing temperature gradient relative to the raw material/crucible is achieved to melt the raw material, and growing, at a predetermined crystal growth length, the material to achieve a monocrystalline crystal, wherein monocrystalline ingots having reduced micro-pit densities are reproducibly provided.

Abstract: Systems, methods, and substrates directed to growth of monocrystalline germanium (Ge) crystals are disclosed. In one exemplary implementation, there is provided a method for growing a monocrystalline germanium (Ge) crystal. Moreover, the method may include loading first raw Ge material into a crucible, loading second raw Ge material into a container for supplementing the Ge melt material, sealing the crucible and the container in an ampoule, placing the ampoule with the crucible into a crystal growth furnace, as well as melting the first and second raw Ge material and controlling the crystallizing temperature gradient of the melt to reproducibly provide monocrystalline germanium ingots with improved/desired characteristics.

Abstract: Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.

Abstract: Chemical polishing solutions and methods are disclosed for the chemical polishing of GaAs wafers. An exemplary chemical polishing solution consistent with the innovations herein may comprise dichloroisocyanurate, sulfonate, acid pyrophosphate, bicarbonate and carbonate. An exemplary chemical polishing method may comprise polishing a wafer in a chemical polishing apparatus in the presence of such a chemical polishing solution. Chemical polishing solutions and methods herein make it possible, for example, to improve wafer quality, decrease costs, and/or reduce environmental pollution.

Abstract: Systems and methods are disclosed for crystal growth using VGF and VB growth processes to reduce body lineage. In one exemplary embodiment, there is provided a method of inserting an ampoule with raw material into a furnace having a heating source, growing a crystal using a vertical gradient freeze process wherein the crystallizing temperature gradient is moved relative to the crystal and/or furnace to melt the raw material and reform it as a monocrystalline compound, and growing the crystal using a vertical Bridgman process on the wherein the ampoule/heating source are moved relative each other to continue to melt the raw material and reform it as a monocrystalline compound.

Abstract: Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.

Abstract: Systems and methods are disclosed for crystal growth including features of reducing micropit cavity density in grown germanium crystals. In one exemplary implementation, there is provided a method of inserting an ampoule with raw material into a furnace having a heating source, growing a crystal using a vertical growth process wherein movement of a crystallizing temperature gradient relative to the raw material/crucible is achieved to melt the raw material, and growing, at a predetermined crystal growth length, the material to achieve a monocrystalline crystal, wherein monocrystalline ingots having reduced micro-pit densities are reproducibly provided.

Abstract: Chemical polishing solutions and methods are disclosed for the chemical polishing of GaAs wafers. An exemplary chemical polishing solution consistent with the innovations herein may comprise dichloroisocyanurate, sulfonate, acid pyrophosphate, bicarbonate and carbonate. An exemplary chemical polishing method may comprise polishing a wafer in a chemical polishing apparatus in the presence of such a chemical polishing solution. Chemical polishing solutions and methods herein make it possible, for example, to improve wafer quality, decrease costs, and/or reduce environmental pollution.

Abstract: Systems, methods, and substrates directed to growth of monocrystalline germanium (Ge) crystals are disclosed. In one exemplary implementation, there is provided a method for growing a monocrystalline germanium (Ge) crystal. Moreover, the method may include loading first raw Ge material into a crucible, loading second raw Ge material into a container for supplementing the Ge melt material, sealing the crucible and the container in an ampoule, placing the ampoule with the crucible into a crystal growth furnace, as well as melting the first and second raw Ge material and controlling the crystallizing temperature gradient of the melt to reproducibly provide monocrystalline germanium ingots with improved/desired characteristics.

Abstract: A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.

Abstract: A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.

Abstract: A system and method for adjustable laser mark depth is provided. In one embodiment, the system is used in Nd—YAG laser marker for wafer processing in the semiconductor industry, with smart control of the mark depth and expanded work range between the deep mark and the light mark.

Abstract: An apparatus and method of treating multiple wafers to reduce the density of impurities as well as to improve the uniformity of substrate electrical characteristics without any thermal stress. The wafers are chemically treated, and heat treated in a sealed reaction tube under arsenic overpressure with a controlled thermal profile to heat the wafers. The thermal profile controls temperature of different zones inside of a furnace containing the sealed reaction tube. Impurities of the wafers are dissolved, and are out-diffused from the inner portions to the outer portions of the wafers.

Abstract: Group III-V, II-VI and related monocrystalline compounds are grown with a rigid support of a sealed ampoule, carbon doping and resistivity control, and thermal gradient control in a crystal growth furnace. A support cylinder provides structural support for the combined sealed ampoule crucible assembly, while low-density insulating material inside the support cylinder deters convection and conduction heating. Radiation channels penetrating the low-density material provide pathways for radiation heating into and out of the seed well and transition regions of the crystal growth crucible. A hollow core in the insulation material directly beneath the seed well provides cooling in the center of the growing crystal, which enables uniform, level growth of the crystal ingot and a flat crystal-melt interface which results in crystal wafers with uniform electrical properties.

Abstract: A high power, high luminous flux light emitting diode (LED) comprises a substrate, a light-emitting structure, a first electrode and a second electrode. The LED has a top surface layout design in which the first electrode has a number of legs extending in one direction, and the second electrode has a number of legs extending in the opposite direction. At least portions of the legs of the first electrode are interspersed with and spaced apart from portions of the legs of the second electrode. This provides a configuration that enhances current spreading along the length of the legs of both electrodes.