Patents Assigned to AyDeeKay
  • Publication number: 20250222935
    Abstract: An integrated circuit for use in a first vehicle may include: an interface circuit that communicates with a second integrated circuit in a second vehicle; and a processing circuit. During operation, the processing circuit may determine that the second vehicle has better situational awareness for a portion of a road or an environment proximate to the road than the first vehicle, where the second vehicle is proximate to the first vehicle. Then, the processing circuit may dynamically establish, with the second integrated circuit, a communication pairing with the second vehicle. Moreover, the integrated circuit may exchange, via the pairing, information with the second integrated circuit. For example, the exchanged information may include or may specify: measurement data, one or more detected objects, one or more object identifiers, seed information for a detection technique (such as a priori information), and/or a priority or urgency of the exchanged information.
    Type: Application
    Filed: March 26, 2025
    Publication date: July 10, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Ichiro Aoki, Shmuel Silverman, Steven Elliot Stupp
  • Patent number: 12339794
    Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: June 24, 2025
    Assignee: AyDeeKay
    Inventor: Scott David Kee
  • Publication number: 20250199976
    Abstract: Embodiments of an integrated circuit are described. This integrated circuit may include a Universal Data Bus Serializer. Moreover, the Universal Data Bus Serializer may include: an input to receive data for transmission over a data bus of a vehicle; memory storing a plurality of protocol operating instructions, where each protocol operating instruction corresponds to a given operating protocol; a selection unit, coupled to the input and the memory, that chooses one of the plurality of protocol operating instructions based on a given protocol; and a serial data output to couple to the data bus and to output serial data based at least in part on the given protocol.
    Type: Application
    Filed: December 12, 2024
    Publication date: June 19, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Rakhel Parida, Andrew Davidson, Tibor Antus, Peter Halasi
  • Patent number: 12275414
    Abstract: An integrated circuit for use in a first vehicle may include: an interface circuit that communicates with a second integrated circuit in a second vehicle; and a processing circuit. During operation, the processing circuit may determine that the second vehicle has better situational awareness for a portion of a road or an environment proximate to the road than the first vehicle, where the second vehicle is proximate to the first vehicle. Then, the processing circuit may dynamically establish, with the second integrated circuit, a communication pairing with the second vehicle. Moreover, the integrated circuit may exchange, via the pairing, information with the second integrated circuit. For example, the exchanged information may include or may specify: measurement data, one or more detected objects, one or more object identifiers, seed information for a detection technique (such as a priori information), and/or a priority or urgency of the exchanged information.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: April 15, 2025
    Assignee: AyDeeKay LLC
    Inventors: Ichiro Aoki, Shmuel Silverman, Steven Elliot Stupp
  • Patent number: 12270938
    Abstract: Disclosed active reflector apparatus and methods that inhibit self-induced oscillation. One illustrative apparatus embodiment includes an amplifier and an adjustable phase shifter. The amplifier amplifies a receive signal to generate a transmit signal, the transmit signal causing interference with the receive signal. The adjustable phase shifter modifies the phase of the transmit signal relative to that of the receive signal to inhibit oscillation. A controller may periodically test a range of settings for the adjustable phase shifter to identify undesirable phase shifts prone to self-induced oscillation, and may maintain the phase shift setting at a value that inhibits oscillation.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: April 8, 2025
    Assignee: AyDeeKay LLC
    Inventors: Tom Heller, Danny Elad
  • Publication number: 20250110203
    Abstract: An integrated circuit is described. This integrated circuit may include multiple stages. At a given time, the integrated circuit may be configured to use one or more of the stages in the processing of received signals associated with measurements in an environment. For example, a control circuit or control logic in the integrated circuit may configure the use of one or more of the stages in the integrated circuit. A first stage in the stages may perform coherent interference mitigation by correcting the received signals for a predicted complex signal associated with a spurious source. Moreover, a second stage in the stages may perform equalization of the received signals based at least in part on a target criterion. Furthermore, a third stage in the stages may combine different received signals (such as received signals associated with different measurements) and may detect one or more peaks in the received signals.
    Type: Application
    Filed: September 27, 2024
    Publication date: April 3, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventor: Facundo Picco
  • Publication number: 20250096812
    Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 20, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Setu Mohta, Christopher A. Menkus, David Kang
  • Publication number: 20250088284
    Abstract: An integrated circuit is described. This integrated circuit may include an optical transmit circuit that outputs optical signals (such as optical pulses or FMCW optical signals) having a carrier-frequency (or chirp) pattern as a function of time, where a modulation signal, associated with an optical source and corresponding to the carrier-frequency pattern, includes a predistortion to reduce a nonlinearity associated with the optical transmit circuit. Moreover, the integrated circuit may include a feedback circuit that measures the nonlinearity (e.g., using an interferometer) and that dynamically adjusts the predistortion based at least in part on the measured nonlinearity. Note that the integrated circuit may provide closed-loop adjustment of the predistortion. In some embodiments, the correction of the nonlinearity may be performed in the frequency domain.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 13, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Facundo Picco, Iván Dipre
  • Publication number: 20250074347
    Abstract: A centralized occupancy detection system enables monitoring of multiple seats, or more generally, multiple stations, with a single sensor. One illustrative vehicle includes: one or more stations each configured to accommodate an occupant of the vehicle, a radar-reflective surface, and a radar transceiver configured to use the radar-reflective surface to detect an occupant of at least one of the stations. Another illustrative vehicle includes: multiple stations to each accommodate an occupant of the vehicle, and a radar transceiver configured to examine each of the multiple stations to determine whether that station has an occupant.
    Type: Application
    Filed: November 17, 2024
    Publication date: March 6, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Danny Elad, Dan Corcos
  • Publication number: 20250047135
    Abstract: An integrated circuit is described. This integrated circuit may include wireless-charger transmitter. The wireless-charger transmitter includes a driver circuit. Moreover, the wireless-charger transmitter selectively filters out an interference signal in a band of frequencies corresponding to AM radio. Note that the selective filtering may be performed by at least a filtering circuit. For example, the filtering circuit may include a low-pass filter. Moreover, the selective filtering using the filtering circuit may be based at least in part on a switching frequency of the wireless-charger transmitter. Furthermore, a filtering frequency associated with the filtering circuit (such as a 3 dB cutoff frequency of a low-pass filter) may be adjusted by selectively electrically coupling a set of capacitors in parallel with the filtering circuit.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 6, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Andrew F. Pinkos, Jeff Patterson, Piotr Strycharski
  • Publication number: 20250030425
    Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 23, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventor: Robert W Kim
  • Patent number: 12204022
    Abstract: A radar system that can block false echoes includes: a local oscillator configured to generate a chirp signal comprising a plurality of chirps, each having a corresponding envelope; a transmitter configured to transmit a signal corresponding to the chirp signal; and a modulation circuit configured to modulate the transmitted signal by regulating a magnitude of one or more portions of the chirp envelopes in a predetermined pattern such that the radar system can discern false echoes which do not match the pattern.
    Type: Grant
    Filed: October 22, 2022
    Date of Patent: January 21, 2025
    Assignee: AyDeeKay LLC
    Inventors: Jian Bai, Nader Rohani
  • Publication number: 20250020801
    Abstract: An integrated circuit that performs multiple separate types of measurements is described. This integrated circuit may include a measurement circuit. Moreover, the integrated circuit may include or may be electrically coupled to at least one sensor. During operation, the integrated circuit may perform the separate types of measurements of or associated with an object in an environment with reduced or obscured information in a visual band of frequencies. For example, the environment with reduced or obscured information may include fog or a cloud. Note that performing of the separate types of measurements may include: filtering measurements based at least in part on velocity relative to ground; and providing data streams having different spatial frequencies and sampling rates based at least in part on the filtering.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 16, 2025
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: David Palmer, Setu Mohta
  • Patent number: 12189019
    Abstract: In an illustrative integrated circuit, a chirp generator provides a chirp signal having linearly-ramped chirp intervals, while a shift frequency generator provides a signal having a different shift frequency during each of multiple segments in each chirp interval. A modulator combines the signals to derive a segmented chirp signal having multiple linearly-ramped chirp segments in each chirp interval. The modulator may be a single sideband modulator to provide frequency up-shifted and frequency down-shifted chirp segments. The segmented chirp signal may be suppressed during resettling intervals of the original chirp signal.
    Type: Grant
    Filed: January 30, 2024
    Date of Patent: January 7, 2025
    Assignee: AyDeeKay LLC
    Inventor: Tom Heller
  • Patent number: 12169464
    Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
    Type: Grant
    Filed: March 26, 2022
    Date of Patent: December 17, 2024
    Assignee: AyDeeKay LLC
    Inventor: Scott David Kee
  • Publication number: 20240385667
    Abstract: An integrated circuit that dynamically adapts power to be provided by at least a first node in network is described. This integrated circuit may include a control circuit (or control logic) that performs the operations of: receiving charging information associated with one or more nodes in the network; determining, based at least in part on the charging information, a dynamic power to be supplied to an electronic device by at least the first node in the one or more nodes; and providing, addressed to at least the first node, an instruction specifying or indicating the dynamic power of at least the first node at a given time.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Robert Martin Voto, Shyambabu Yeda, Chenpeng Mu
  • Patent number: 12136924
    Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
    Type: Grant
    Filed: October 3, 2023
    Date of Patent: November 5, 2024
    Assignee: AyDeeKay LLC
    Inventor: Robert W Kim
  • Publication number: 20240340019
    Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventors: Christopher A. Menkus, Robert W. Kim
  • Patent number: 12085664
    Abstract: Automotive radar methods and systems for enhancing resistance to interference using a built-in self-test (BIST) module. In one illustrative embodiment, an automotive radar transceiver includes: a signal generator that generates a transmit signal; a modulator that derives a modulated signal from the transmit signal using at least one of phase and amplitude modulation; at least one receiver that mixes the transmit signal with a receive signal to produce a down-converted signal, the receive signal including the modulated signal during a built-in self-test (BIST) mode of operation; and at least one transmitter that drives a radar antenna with a selectable one of the transmit signal and the modulated signal.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: September 10, 2024
    Assignee: AyDeeKay LLC
    Inventor: Tom Heller
  • Publication number: 20240291436
    Abstract: An integrated circuit that selectively filters out common-mode and differential signals is described. This integrated circuit may include an RF receiver with a mixer that converts signals between a band of frequencies in the RF and a second band of frequencies based at least in part on second signals, where the second band of frequencies is less than the band of frequencies. Moreover, the mixer may include input ports that receive the second signals and include a filter circuit, electrically coupled in parallel with the input ports, that filters out the common-mode signals above a threshold frequency and filters out the differential signals below the threshold frequency. For example, the filter circuit may include a half-wavelength transmission line. Note that the mixer may convert the differential signals to the common-mode signals below the threshold frequency and may convert the common-mode signals to the differential signals above the threshold frequency.
    Type: Application
    Filed: February 23, 2024
    Publication date: August 29, 2024
    Applicant: AyDeeKay LLC dba Indie Semiconductor
    Inventor: Benny Sheinman