Abstract: An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.

Abstract: An integrated circuit may include K transmit circuits that output K transmit signals, where K is a non-zero integer and the K transmit signals are encoded using first Doppler code multiplexing. Moreover, the integrated circuit may include L receive circuits that provide L receive signals (which may correspond to the K transmit signals), where L is a non-zero integer and the L receive signals are encoded using second Doppler code multiplexing. Note that the first and/or the second Doppler code multiplexing may be different from Doppler division multiplexing. Furthermore, the first Doppler code multiplexing may include selectively Doppler shifting a kth transmit signal in the K transmit signals by nk bins between chirps in a frame, and the second Doppler code multiplexing may include selectively Doppler shifting an lth receive signal in the L transmit signals by n1 bins between the chirps in the frame.

Abstract: An integrated circuit is described. This integrated circuit may include a wireless-charger transmitter, which includes a driver circuit electrically coupled to multiple branches associated with multiple transmission coils. A given branch may include or may be electrically coupled to: a capacitor, a multiplexor (MUX) switch that includes a single field-effect transistor (FET) or a single integrated-gate bipolar transistor (IGBT), and a given transmission coil. Moreover, the wireless-charger transmitter may include a control circuit that provides control signals to gates of FETs or the IGBTs in the branches that selectively activate at least the MUX switch in the given branch and selectively deactivate remaining MUX switches in a remainder of the branches. Furthermore, the driver circuit may perform wireless charging by driving the given transmission coil in the activated given branch using an electrical signal having a fundamental frequency component.

Abstract: An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.

Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

Abstract: An integrated circuit for use in a first vehicle may include: an interface circuit that communicates with a second integrated circuit in a second vehicle; and a processing circuit. During operation, the processing circuit may determine that the second vehicle has better situational awareness for a portion of a road or an environment proximate to the road than the first vehicle, where the second vehicle is proximate to the first vehicle. Then, the processing circuit may dynamically establish, with the second integrated circuit, a communication pairing with the second vehicle. Moreover, the integrated circuit may exchange, via the pairing, information with the second integrated circuit. For example, the exchanged information may include or may specify: measurement data, one or more detected objects, one or more object identifiers, seed information for a detection technique (such as a priori information), and/or a priority or urgency of the exchanged information.

Abstract: Disclosed active reflector apparatus and methods that inhibit self-induced oscillation. One illustrative apparatus embodiment includes an amplifier and an adjustable phase shifter. The amplifier amplifies a receive signal to generate a transmit signal, the transmit signal causing interference with the receive signal. The adjustable phase shifter modifies the phase of the transmit signal relative to that of the receive signal to inhibit oscillation. A controller may periodically test a range of settings for the adjustable phase shifter to identify undesirable phase shifts prone to self-induced oscillation, and may maintain the phase shift setting at a value that inhibits oscillation.

Abstract: A radar system that can block false echoes includes: a local oscillator configured to generate a chirp signal comprising a plurality of chirps, each having a corresponding envelope; a transmitter configured to transmit a signal corresponding to the chirp signal; and a modulation circuit configured to modulate the transmitted signal by regulating a magnitude of one or more portions of the chirp envelopes in a predetermined pattern such that the radar system can discern false echoes which do not match the pattern.

Abstract: In an illustrative integrated circuit, a chirp generator provides a chirp signal having linearly-ramped chirp intervals, while a shift frequency generator provides a signal having a different shift frequency during each of multiple segments in each chirp interval. A modulator combines the signals to derive a segmented chirp signal having multiple linearly-ramped chirp segments in each chirp interval. The modulator may be a single sideband modulator to provide frequency up-shifted and frequency down-shifted chirp segments. The segmented chirp signal may be suppressed during resettling intervals of the original chirp signal.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: Automotive radar methods and systems for enhancing resistance to interference using a built-in self-test (BIST) module. In one illustrative embodiment, an automotive radar transceiver includes: a signal generator that generates a transmit signal; a modulator that derives a modulated signal from the transmit signal using at least one of phase and amplitude modulation; at least one receiver that mixes the transmit signal with a receive signal to produce a down-converted signal, the receive signal including the modulated signal during a built-in self-test (BIST) mode of operation; and at least one transmitter that drives a radar antenna with a selectable one of the transmit signal and the modulated signal.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.

Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.

Abstract: An automotive radar system includes multiple radar antennas and a radar front end chip. The front end chip includes a plurality of phase rotators coupled to a local oscillator, wherein each phase rotator of the plurality of phase rotators is coupled to multiple digital phase modulators; a plurality of switches that couple selectable ones of the multiple digital phase modulators to respective amplifiers, each amplifier coupled to a respective antenna output; and a controller which provides digital control signals to the plurality of phase rotators, the multiple digital phase modulators, and the plurality of switches to synthesize transmit signals for each of the multiple radar antennas.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.