Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A semiconductor device comprising a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on the substrate; and a MOS structure formed on the epitaxial layer; said MOS structure including multiple well regions with a second conductivity type; multiple source regions with highly doped first conductivity type formed in the well regions; multiple highly doped regions of the second conductivity type formed in the well regions; an insulating gate oxide layer formed on top of the epitaxial layer and spanned adjacent wells and source regions; and a gate electrode formed above the gate oxide layer and spanned adjacent wells and source regions, wherein a JFET region is formed between two adjacent wells; and one or more central implant regions are added with the second conductivity type on a surface of the JFET region to reduce an electric field in the gate oxide.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A semiconductor device may include a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on one side of the substrate; a plurality of regions having a second conductivity type formed under a top surface of the epitaxial layer; a first Ohmic metal patterned and deposited on top of the regions with the second conductivity type; a Schottky contact metal deposited on top of the entire epitaxial layer to form a Schottky junction; and a second Ohmic metal deposited on a backside of the substrate, wherein the regions include one or more wide regions, each having different widths that can be optimized to simultaneously obtain high surge current capability and preserve a low forward voltage drop and reverse leakage current.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A power converter may include a plurality of inductor banks; a plurality of capacitor banks; a plurality of switches, each switch having two power nodes and one control node that receives a control signal that maintains the switch in either ON state in which the circuit path between the first node and the second node are established, or OFF state in which the circuit path between the first node and the second node are eliminated; and a control logic that generates multiple signal combinations that are applied to the control nodes of the switches so that for each signal combination the power converter is configured to generate different voltage outputs. In one embodiment, the control logic generates control signals to cause zero current switching on each switch.

Abstract: In one aspect, a power converter may include a plurality of inductor banks; a plurality of switches, each switch has a first power node and a second power node, and one control node that receives a control signal that maintains the switch in either ON state in which the circuit path between the first node and the second node are established, or OFF state in which the circuit path between the first node and the second node are eliminated; and a control logic that generates multiple signals that are applied to the control nodes of the switches. In one embodiment, the switches are MOSFETs; the first power nodes are drains and the second power nodes are sources, and the control nodes are gates.

Abstract: A power converter may include a plurality of inductor banks; a plurality of capacitor banks; an intermediate bus capacitor bank; a plurality of switches, each switch has a first power node, a second power node and one control nodes that receives a control signal that maintains the switch in either ON state in which the circuit path between the first power node and the second power node are established, or OFF state in which the circuit path between the first power node and the second power node are eliminated, and a control logic that generates a plurality of signal combinations that are applied to the control nodes of said plurality of switches to enable the power converter to have a smooth voltage output and enhanced tolerance for a low voltage input bus for all signal combinations.

Abstract: In one aspect, a power converter may include a plurality of inductor banks; a plurality of capacitor banks; an intermediate bus capacitor bank; a plurality of switches, each switch has a first power node and a second power node, and one control node that receives a control signal that maintains the switch in either ON state in which the circuit path between the first node and the second node are established, or OFF state in which the circuit path between the first node and the second node are eliminated; and a control logic that generates a plurality of signal combinations that are applied to the control nodes of said plurality of switches to enable the power converter to have a smooth voltage output and enhanced tolerance for a low voltage input bus for all signal combinations.

Abstract: A method for manufacturing a Silicon Carbide (SiC) Schottky diode may include steps of providing a substrate; forming a first epitaxial layer with a first conductivity type on top of the substrate; forming a second epitaxial layer with a second conductivity type on top of the first epitaxial layer; forming a third epitaxial layer with the second conductivity type on top of the second epitaxial layer; patterning and etching the second and third epitaxial layers to form a plurality of trenches; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the second epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal.

Abstract: In one aspect, a semiconductor device may include a semiconductor substrate formed of silicon carbide; and an edge termination having a first metal layer and a second metal layer, wherein the first metal layer is deposited and patterned spacedly on the semiconductor substrate and the second metal layer is deposited and patterned onto at least a portion of the spaced first metal layer and onto the semiconductor substrate between said spaced first metal layer, and wherein the first metal layer comprises a high work function metal, while the second metal layer comprises a low work function metal. In one embodiment, the high work function metal includes Silver, Aluminum, Chromium, Nickel, and Gold; and the low work function metal includes Titanium and Nickel Silicide.

Abstract: In one aspect, a merged PiN Schottky (MPS) diode may include a silicon carbide substrate having a first conductivity type. The epitaxial layer with a first conductivity type was formed on the substrate, which has doping concentration lower than the substrate. A plurality of regions having the second conductivity type different from the first conductivity type are formed under the surface of the epitaxial layer. The Ohmic contact metal is formed on the region of the second conductivity type. The Schottky contact metal is placed on top of the entire epitaxial layer to form a Schottky junction. The Ohmic contact was formed by a cathode electrode on the back side of the substrate.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: In one aspect, a method for manufacturing an analog integrated circuit with improved transistor lifetime includes steps of: providing a P-type substrate; forming N+ source/drain regions; forming a P+ isolation island to separate a high voltage I/O transistor and low voltage core transistor; patterning a SiON dielectric layer on one side of the P+ isolation island for the high voltage I/O transistor; patterning a SiO2 dielectric layer on the other side of the P+ isolation island for the low voltage core transistor; forming a gate structure for the low voltage core transistor and high voltage I/O transistor; forming a gate polysilicon layer on a top portion of each of the SiO2 and SiON dielectric layers; forming a SiON passivation layer with open holes; and forming a source electrode, a gate electrode and a drain electrode for each of the low voltage core transistor and high voltage I/O transistor.

Abstract: A Schottky diode may include a substrate; an epitaxial layer deposited on top of the substrate; one or more trenches formed on top of the epitaxial layer; an implantation region at a bottom portion of each trench; an ohmic contact metal on the other side of the substrate; a first Schottky contact metal deposited onto the implantation region in each trench to form a first Schottky junction between the first Schottky contact metal and the epitaxial layer at a lower trench sidewall; a second Schottky contact metal filling each trench and extending a predetermined length to each corner of mesas on the epitaxial layer to form a second Schottky junction between the second Schottky contact metal and the epitaxial layer at an upper trench sidewall; and a third Schottky contact metal covering the second Schottky contact metal and the epitaxial layer to form a third Schottky junction.

Abstract: In one aspect, a method for manufacturing a silicon carbide (SiC) multi-Schottky-layer trench junction barrier Schottky diode may include steps of providing a substrate; forming an epitaxial layer on top of the substrate; forming one or more trenches on the epitaxial layer; generating a first implantation region at a bottom portion of each trench; providing an ohmic contact metal on an opposite of the substrate; generating a second implantation region at each corner near a top portion of each trench; and forming a Schottky contact metal to fill in each trench and on top of the epitaxial layer.

Abstract: In one aspect, a semiconductor device may include a semiconductor substrate formed of silicon carbide; and an edge termination having a first metal layer and a second metal layer, wherein the first metal layer is deposited and patterned spacedly on the semiconductor substrate and the second metal layer is deposited and patterned onto at least a portion of the spaced first metal layer and onto the semiconductor substrate between said spaced first metal layer, and wherein the first metal layer comprises a high work function metal, while the second metal layer comprises a low work function metal. In one embodiment, the high work function metal includes Silver, Aluminum, Chromium, Nickel, and Gold; and the low work function metal includes Titanium and Nickel Silicide.

Abstract: In one aspect, a semiconductor device comprising an electronic conductive Silicon Carbide (SiC) substrate; a semi-insulating or insulating SiC epitaxial layer formed on the electronic conductive SiC substrate; and a Gallium Nitride (GaN) device formed on the semi-insulating or insulating SiC epitaxial layer. In one embodiment, the semi-insulating or insulating SiC epitaxial layer is grown directly on the SiC substrate through chemical vapor deposition (CVD). In another embodiment, the GaN device is a high electron mobility transistor (HEMT).

Abstract: A manufacturing method for a LDMOS semiconductor device may include steps of forming a P-type layer on a P-type substrate; forming a P-type body region and an N-type well under the P-type layer; forming a field oxide on the P-type layer; forming a gate oxide on the P-type body region and field oxide; forming a gate polysilicon on top of the gate oxide; depositing a gate metal silicide on top of the gate polysilicon; depositing a thin film on top of the field oxide, P-type body region and gate silicide; forming a dielectric layer on top of the thin film; forming a first trench in the dielectric layer; forming a second trench underneath the first trench; depositing a metal layer on top of the dielectric layer and filling into the first and second trenches; and removing the metal on top of the dielectric layer.