Abstract: In accordance with one embodiment of the present invention, a non-volatile integrated circuit memory includes a flash EPROM array having a first plurality of memory cells, and an EEPROM array having a second plurality of memory cells arranged along rows and columns. Each of the first and second plurality of memory cells has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a floating gate and a select gate. The EEPROM array further includes a plurality of data lines each being coupled to the drain regions of a plurality of cells along at least a portion of a column of cells, and a plurality of source lines each being coupled to the source regions of a plurality of cells along at least a portion of a row of cells.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: In accordance with an embodiment of the present invention, an array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a stack of floating gate and select gate extending over the channel region, the select gate of the cells along each row being connected together to form a wordline. Each of a plurality of data lines is coupled to the drain region of at least a portion of a column of cells.

Abstract: A portable wireless storage unit for storing data includes a radio-frequency (RF) module, a microprocessor module, a main memory module, and a power control module. The RF module enables wireless communication between the wireless storage unit and a target device, the wireless communication including data transfer requests and data. The microprocessor module processes data transfer requests received by the RF module. The main storage module, which includes a main memory, responds to data transfer requests under control of the microprocessor module by retrieving data from the main memory for transmission by the RF module and by storing data received by the RF module in the main memory. The power control module, which can be coupled to a power source, selectively supplies power to one or more of the RF module, the main storage module, and the microprocessor module.

Abstract: In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

Abstract: In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

Abstract: In accordance with one embodiment of the present invention, a non-volatile integrated circuit memory includes a flash EPROM array having a first plurality of memory cells, and an EEPROM array having a second plurality of memory cells arranged along rows and columns. Each of the first and second plurality of memory cells has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a floating gate and a select gate. The EEPROM array further includes a plurality of data lines each being coupled to the drain regions of a plurality of cells along at least a portion of a column of cells, and a plurality of source lines each being coupled to the source regions of a plurality of cells along at least a portion of a row of cells.

Abstract: In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.

Abstract: In accordance with an embodiment of the present invention, an array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a stack of floating gate and select gate extending over the channel region, the select gate of the cells along each row being connected together to form a wordline. Each of a plurality of data lines is coupled to the drain region of at least a portion of a column of cells.

Abstract: An array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further includes a stack of floating gate and select gate extending over the channel region. The select gate of the cells along each row are connected together to form a wordline. Each of a number of data lines is coupled to the drain regions of at least a portion of a column of cells. Each of a number of source lines is coupled to a source region of a plurality of cells along at least a portion of a row of cells. In such a memory array, a selected memory cell is biased so that a threshold voltage of the selected memory cell is increased by injection of hot electrons from a portion of the channel region near the source region to the floating gate.

Abstract: A semiconductor wafer has a plurality of dies separated by scribe line areas. Each die has a first pad for receiving a power supply voltage and a second pad for receiving a ground potential. The scribe line areas include at least a first metal line and a second metal line respectively connected to the first pad and the second pad of each of the plurality of dies. A probe card is brought into contact with a first die to initiate a built-in self test (BIST) in the first die. Once the BIST operation is properly initiated, the probe card is moved to a second die to similarly initiate the BIST operation in the second die. The probe card is moved from the first die to the second die while the BIST operation in first die is in progress. In this manner, the BIST operation in multiple dies overlap, thus reducing the overall wafer sort testing time compared to the conventional method of sequential testing of dies.

Abstract: A semiconductor wafer has a plurality of dies separated by scribe line areas. Each die has a first pad for receiving a power supply voltage and a second pad for receiving a ground potential. The scribe line areas include at least a first metal line and a second metal line respectively connected to the first pad and the second pad of each of the plurality of dies. A probe card is brought into contact with a first die to initiate a built-in self test (BIST) in the first die. Once the BIST operation is properly initiated, the probe card is moved to a second die to similarly initiate the BIST operation in the second die. The probe card is moved from the first die to the second die while the BIST operation in first die is in progress. In this manner, the BIST operation in multiple dies overlap, thus reducing the overall wafer sort testing time compared to the conventional method of sequential testing of dies.

Abstract: A flash memory device and its method of operation provide for selective, e.g., bit-by-bit, erase operation resulting in much narrower distribution for erase threshold voltage VTE. Latches that couple to the array are set or reset depending on cell content during erase verify. The output of the latches are then applied to selected cells to perform erase. The flash architecture allows for bit-by-bit erase verify operation resulting in a tighter VTE distribution and elimination of the need for preprogramming. In a preferred embodiment, the flash cell is programmed by CHE tunneling and erased by FN tunneling both occurring on the same side (e.g., drain side) of the cell transistor.

Abstract: In accordance with the present invention, a low VCC operational non-volatile memory cell includes a drain region and a source region separated by a channel region. A tunneling dielectric layer extends over the channel region and a portion of the drain and source regions. A floating gate extends over the tunneling dielectric. An insulating layer extends over the floating gate, and a control gate extends over the insulating layer. The channel region is implanted with a relatively low dosage of channel threshold enhancement impurities or halo impurities to obtain a low initial Vt in the range of, for example, OV to 0.8V. The low initial Vt enables a low program Vt target ,e.g., 4V or less, which in turn enables the use of double-diffused N+, N− drain or source junctions with the N+ region being inside the N− region.