Patents Assigned to Azul Systems, Inc.
  • Patent number: 11294791
    Abstract: A first instance of a managed runtime environment is provided. An optimized version of a code unit and a corresponding set of one or more speculative assumptions are received at the first instance of the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, and wherein the optimized version of the code unit and the corresponding set of one or more speculative assumptions are generated by an entity that is different from the first instance of the managed runtime environment. The optimized version of the code unit is executed at the first instance of the managed runtime environment. Whether the set of one or more speculative assumptions hold true is monitored at the first instance of the managed runtime environment.
    Type: Grant
    Filed: October 17, 2020
    Date of Patent: April 5, 2022
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Philip Reames
  • Patent number: 11029930
    Abstract: A method of providing by a code optimization service an optimized version of a code unit to a managed runtime environment is disclosed. Information related to one or more runtime conditions associated with the managed runtime environment that is executing in a different process than that of the code optimization service is obtained, wherein the one or more runtime conditions are subject to change during the execution of the code unit. The optimized version of the code unit and a corresponding set of one or more speculative assumptions are provided to the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, wherein the set of one or more speculative assumptions are based on the information related to the one or more runtime conditions.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: June 8, 2021
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Philip Reames
  • Patent number: 10846196
    Abstract: A first instance of a managed runtime environment is provided. An optimized version of a code unit and a corresponding set of one or more speculative assumptions are received at the first instance of the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, and wherein the optimized version of the code unit and the corresponding set of one or more speculative assumptions are generated by an entity that is different from the first instance of the managed runtime environment. The optimized version of the code unit is executed at the first instance of the managed runtime environment. Whether the set of one or more speculative assumptions hold true is monitored at the first instance of the managed runtime environment.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 24, 2020
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Philip Reames
  • Patent number: 10671400
    Abstract: A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 10552130
    Abstract: A method of providing by a code optimization service an optimized version of a code unit to a managed runtime environment is disclosed. Information related to one or more runtime conditions associated with the managed runtime environment that is executing in a different process than that of the code optimization service is obtained, wherein the one or more runtime conditions are subject to change during the execution of the code unit. The optimized version of the code unit and a corresponding set of one or more speculative assumptions are provided to the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, wherein the set of one or more speculative assumptions are based on the information related to the one or more runtime conditions.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 4, 2020
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Philip Reames
  • Patent number: 9928071
    Abstract: A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and commit at least some of the one or more memory modification instructions. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: March 27, 2018
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 9928072
    Abstract: A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units is not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and establish an incidentally atomic sequence of instruction units based at least in part on detection of the atomicity terminating event, wherein the incidentally atomic sequence of instruction units correspond to a sequence of instruction units in the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: March 27, 2018
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 9645795
    Abstract: Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: May 9, 2017
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Murali Sundaresan, Michael A. Wolf
  • Patent number: 9594659
    Abstract: Indicating usage in a system includes implementing a performance counter associated with one or more hardware threads; counting events associated with the one or more hardware threads to determine an event count; deriving an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count; applying a corrective function to modify the initial measure of usage and determine a modified measure of usage, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and outputting an indication of a processor usage, the indication being based at least in part on the modified measure of usage.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: March 14, 2017
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 9361114
    Abstract: Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: June 7, 2016
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Scott Sellers, Jack Choquette, Michael A. Wolf
  • Patent number: 9342319
    Abstract: Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 17, 2016
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Cliff N. Click, Jr., Murali Sundaresan, Michael A. Wolf
  • Patent number: 9336005
    Abstract: Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: May 10, 2016
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Scott Sellers, Jack H. Choquette
  • Patent number: 8990501
    Abstract: A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster including a second plurality of processors associated with a second cluster cache, and a cluster communication network between the first cluster and the second cluster for sharing data between the first cluster and the second cluster. The first cluster includes a first unshared connection to the cluster communication network and the second cluster includes a second unshared connection to the cluster communication network.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: March 24, 2015
    Assignee: Azul Systems, Inc.
    Inventors: Scott Sellers, Gil Tene
  • Patent number: 8949583
    Abstract: Executing a set one or more instructions is disclosed. A set of one or more register states is saved in a software data structure. The set of instructions is speculatively executed. At least one store made to a memory location during the speculative execution is not committed until the speculative execution is successfully completed. If an abort indication is received, the state of one or more registers restored.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: February 3, 2015
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Ivan Posva, Michael A. Wolf, Daniel Dwight Grove, Tom Kraljevic
  • Patent number: 8843944
    Abstract: Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: September 23, 2014
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Murali Sundaresan, Michael A. Wolf
  • Patent number: 8838940
    Abstract: Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread information with information related to a decreasing ability of the processor core to increase throughput by utilizing additional hardware threads, and indicating the usage in the system based at least in part on both the active thread information and the ability of the processor core to increase throughput by utilizing additional hardware threads.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: September 16, 2014
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 8839274
    Abstract: Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: September 16, 2014
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Cliff N. Click, Jr., Murali Sundaresan, Michael A. Wolf
  • Patent number: 8725982
    Abstract: Memory management includes identifying a region of virtual memory to be reclaimed, the region including an object that is currently located at an original virtual memory location, and the region being supported by at least a portion of a memory resource; relocating the object from the original virtual memory location to a target virtual memory location; releasing the portion of the memory resource so that the portion of memory resource can be reused; and after the portion of the memory resource is released, replacing a reference of the object that points to the original virtual memory location with a reference of the object that points to the target virtual memory location.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: May 13, 2014
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf
  • Publication number: 20140082632
    Abstract: Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.
    Type: Application
    Filed: August 9, 2013
    Publication date: March 20, 2014
    Applicant: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Scott Sellers, Jack H. Choquette
  • Publication number: 20130311741
    Abstract: Memory management includes identifying a region of virtual memory to be reclaimed, the region including an object that is currently located at an original virtual memory location, and the region being supported by at least a portion of a memory resource; relocating the object from the original virtual memory location to a target virtual memory location; releasing the portion of the memory resource so that the portion of memory resource can be reused; and after the portion of the memory resource is released, replacing a reference of the object that points to the original virtual memory location with a reference of the object that points to the target virtual memory location.
    Type: Application
    Filed: April 25, 2013
    Publication date: November 21, 2013
    Applicant: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf