Abstract: A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.

Abstract: Improving performance of a computer program is disclosed. A first set of escape data is gathered. A first compiled program is provided using the first set of escape data. A second set of escape data is gathered based on the first compiled program. A second compiled program is provided using the second set of escape data. The second compiled program is more optimized than the first compiled program.

Abstract: Variable-length packets transmitted over a serial link do not have packet-start fields or unique symbols to mark the beginning of each packet. Instead, a length field indicates the packet's length, allowing the end of the packet to be located. Packets also do not have sequence numbers. When an error is detected, the receiver sends a control symbol over a reverse channel to signal the transmitter. The control symbol never occurs in a normal packet. Packet buffers in the transmitter and receiver have read and write pointers and also have de-allocation pointers that are synchronized between receiver and transmitter. As packets are error checked, the receiver advances its de-allocation pointer and updates the transmitter's de-allocation pointer, allowing the packets to be discarded from the transmitter's buffer only after the receiver finishes error checking. The transmitter re-transmits packets from its buffer starting from the de-allocation pointer when its receives the control symbol.

Abstract: Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to all snoop tag partitions on all cluster chips. Each snoop tag partition has all the system's snoop tags for a partition of the main memory space. The snoop index is a subset of the cache index, with remaining chip-select and interleave address bits selecting which of the snoop tag partitions on the multiple cluster chips stores snoop tags for that address. The number of snoop entries in a snoop set is equal to a total number of cache entries in one cache index for all local caches on all cluster chips. Cache coherency request processing is distributed among the snoop tag partitions on different cluster chips, reducing bottlenecks.

Abstract: A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4 bits or less. Rather than generating address parity, which is poor at detecting even numbers of errors, a cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to just 4 address check bits using the CRC code. The 4 address check bits are merged (XOR'ed) with two 4-bit nibbles of the data SbEC/DbED code to generate a merged ECC codeword that is stored in memory. An address error causes a 2-nibble mis-match due to the redundant merging of the 4 address check bits with 2 nibbles of data correction code. The CRC code is ideal for detecting even numbers of errors common with multiplexed-address DRAMs.

Abstract: A technique for managing an object in memory is disclosed. The technique comprises: assigning the object to an assigned frame wherein the object can be released when the assigned frame is released; detecting an attempt to place a reference to the object in an older frame, the older frame being older than the assigned frame; and reassigning the object to a reassignment frame that is at least as old as the older frame.

Abstract: A die with embedded memory is packaged together in a same dual-chip package with an EEPROM die. Defects in the embedded memory can be repaired using redundant rows or columns. A built-in self-test (BIST) controller locates defects and a repair image is generated. The repair image is stored in non-volatile memory in the EEPROM die. At power-up, the repair image is copied from the EEPROM die to a volatile repair RAM in the embedded memory die. The redundant rows or columns are mapped to replace defective rows/columns using the repair image in the volatile repair RAM. Although the embedded-memory die has only volatile memory and no fuses, its embedded memory can be repaired using the repair map from the non-volatile EEPROM die. Since the EEPROM die is in the same dual-chip package as the embedded memory die, the repair map is always available.

Abstract: A system and method are disclosed for a segmented virtual machine. The segmented virtual machine includes a core VM and a shell VM associated with the core VM. The core VM is configured to perform VM internal execution functionality and the shell VM is configured to perform shell VM functions and communicate with the core VM.