Abstract: A method for estimating the average-case activity in a digital circuit includes the steps of identifying one or more predesignated types of circuit elements in the digital circuit, and propagating activity values through any identified circuit elements using a predetermined formula.

Abstract: The present invention provides a method for estimating the average-case activity in a digital circuit. The method includes the steps of assigning initial activity values to outputs of flops in the digital circuit, and repeatedly updating the activity values in an iterative procedure until a predetermined termination criterion is met. The updating of the activity values uses a combination of standard probability updating techniques and predetermined formulae for obtaining the activity values of predesignated types of circuit elements in the digital circuit. The predesignated types of circuit elements include, for example, one or more of a clock-gated flop, an enable flop and a flop with a recirculation multiplexer.

Abstract: A method, graphical user interface, and computer program product on a computer readable medium are disclosed for presenting a user with a display of a skew clock tree for a digital circuit design. In the preferred embodiment, a computer system receives timing analysis data for a digital circuit. The computer system determines a propagation time delay between a first clock root and each of a plurality of clock sinks of the digital circuit associated with the first clock root based on the timing analysis data. The computer system then displays the first clock root and each clock sink associated with the first clock root of the skew clock tree along an axis representing time delay. In the displayed skew clock tree, each clock sink is positioned along the axis relative to the first clock root based on each clock sink's determined propagation time delay.

Abstract: A method for estimating the average-case activity in a digital circuit includes the steps of identifying a state machine in the digital circuit, and propagating activity values through the state machine to obtain activity information at an output of a flop in the state machine using a predetermined formula.

Abstract: A method for estimating the average-case activity in a digital circuit having a clock tree, includes the steps of obtaining seed activity values at various nodes in the digital circuit using a probability-based algorithm, creating waveform traces at various nodes in the digital circuit using the seed activity values, and propagating the waveform traces through the digital circuit to find improved activity values at various nodes in the digital circuit using a simulation-based algorithm.

Abstract: There is disclosed a method, and corresponding apparatus, for determining a clock gating function for a set of clocked state-holding elements, comprising the steps of: for each element, determining the conditions under which the element will hold its current value based only on those inputs which are common to all elements; and combining the conditions to form a gating function.

Abstract: A method for estimating the average-case activity in a digital circuit includes the steps of identifying a state machine in the digital circuit, and propagating activity values through the state machine to obtain activity information at an output of a flop in the state machine using a predetermined formula.

Abstract: A method for estimating the average-case activity in a digital circuit includes the steps of identifying one or more predesignated types of circuit elements in the digital circuit, and propagating activity values through any identified circuit elements using a predetermined formula.

Abstract: A method for estimating the average-case activity in a digital circuit includes the steps of assigning initial activity values to outputs of flops in the digital circuit, and repeatedly updating the activity values in an iterative procedure until a predetermined termination criterion is met, wherein the updating of the activity values uses a combination of standard probability updating techniques and predetermined formulae for obtaining the activity values of predesignated types of circuit elements in the digital circuit.

Abstract: A method of determining a forced gating function for at least one of a plurality of clocked state-holding elements. The forced gating function compares the input and output of said at least one clocked state-holding element. The method simulates the performance of the element for different implementation conditions; measures the performance of the element for each condition, and determines the implementation of the forced gating function using the measured performances.

Abstract: There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

Abstract: A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated circuit design using guard-flops, the method comprising: identifying D-type flip-flops in the first integrated circuit design, and transforming each of the identified D-type flip-flops into a guard-flop comprising a transparent catch latch and a transparent pass latch; generating a catch enable signal for controlling the transparent catch latch from the clock signal and enable signal of the D-type flip-flop in the first integrated circuit design; and generating a pass enable signal for controlling the transparent pass latch based on the catch signals of at least some of the guard-flops that take data from the D-type flip-flop in the first integrated circuit design.

Abstract: A latch is provided which includes: a transparent catch latch having a data input, a data output and a control node arranged to receive a catch signal; a transparent pass latch having a data input connected to the data output of the transparent catch latch at an internal storage node, a data output, and a control node arranged to receive a pass signal; and logic circuitry having an enable input and a clock input connected to provide a gated clock signal to provide one of said catch signal and said pass signal. In another aspect an integrated circuit is provided with input and output guard flops, each including a transparent catch latch and a transparent pass latch, and further including a logic gate with an enable input and a clock input connected to provide a gated clock signal to at least one of the transparent pass latch of the input guard-flop and transparent catch latch of the output guard flop.