Abstract: A method for designing a dual-mode logic circuit which is selectably operational in static and dynamic modes is performed as follows. A basis library with a DML inverter and dual-mode logic (DML) bicells is provided. Each DML bicell includes a type-A DML logic gate with a clock input and a type-B DML logic gate with an inverted clock input. A pseudo-static library is formed from the basis library by modifying each bicell of the basis library and specifying at least one dynamic timing parameter. A dynamic library is formed from the basis library by specifying dynamic timing parameters for the basis library DML inverter and bicells. Logic behavior of the required logic circuit is defined. An initial logic circuit design synthesized from the pseudo-static library and the defined logic behavior. Finally, a dynamic circuit design is formed by replacing modified bicells with corresponding bicells from the dynamic library.