Abstract: A method and apparatus for producing an object (2) comprising providing a digital model (14) of the object (2) that is to be produced; using the digital model, identifying one or more parts (8) of the object (2) that satisfy certain criteria; for each identified part (8), adjusting, in the digital model (14), the thickness of that part (8) to satisfy further criteria, thereby producing an updated model; performing a first production process to produce the part or parts (4, 6) of the object (2) that do not satisfy the criteria, thereby producing an initial object (17); performing an Additive Manufacturing process to add, to the initial object (17), the one or more identified parts (8), thereby producing the object (2). The initial object (17) and identified parts (8) are made of the same material. The first production process is different to the Additive Manufacturing process.

Abstract: A network management assembly is disclosed for managing a flow of network management traffic across a network containing a plurality of discrete network domains. The assembly can include a first management terminal which is arranged to transmit network management traffic to each of the network domains via a respective first communication link, and a second management terminal which is arranged to receive network management traffic from each of the network domains via a respective second communication link. Each of the first communication links can permit a flow of network management traffic from the first management terminal to a respective domain, and prevent a reverse flow of network management traffic from the respective domain to the first management terminal. Each of the second communication links can permit a flow of network management traffic from a respective domain to the second management terminal, and prevent a reverse flow.

Abstract: A health monitoring system for complex networked apparatus includes a number of neuro-fuzzy inference apparatuses feeding inference results into a data fusion hierarchy. At each level in the hierarchy, fuzzy inference is applied to generate a desired output signal by processing selected input signals in accordance with a knowledge base defining fuzzy membership functions and fuzzy inference rules defined in advance. The knowledge base includes alternative definitions of membership functions and/or inference rules. The apparatus selects which definition to use according to environmental or other conditions, and predetermined selection criteria.

Abstract: A controller is provided, operable to control a system on the basis of measurement data received from a plurality of sensors indicative of a state of the system, with at least partial autonomy, but in environments in which it is not possible to fully determine the state of the system on the basis of such sensor measurement data.

Abstract: An acousto-optic module is provided, including a number of partially coupled optical resonators distributed within a dielectric medium and at least one acoustic transducer mounted on a surface of the dielectric medium for injecting an acoustic wave into the optical resonators so as to diffract light passing therethrough by means of Bragg diffraction. This acousto-optic module has been applied in particular to an improved tuneable optical filter in which an acoustic shear wave is generated and which travels through the acousto-optic module in a direction substantially parallel with a polarized light signal passing therethrough. The acousto-optic module is also applied to an improved optical frequency shifter.

Abstract: A specific emitter identification (SEI) method and apparatus is capable of identifying and tracking objects within a geographical area of interest wherein the system and method has not been preprogrammed to look for particular signals. The system and method receives all of the emitted electromagnetic signals emitted from area of interest. The system and method next performs high order statistical analysis on the received signals and determines which signals emanate from possible targets of interest and which likely emanate from background clutter/noise by comparing the relative degrees of Gaussianness of the signals (for example using entropy measurements). The least Gaussian signals are deemed to likely be signals from potential targets of interest while those which are more Gaussian are deemed to be likely from background clutter or noise.

Abstract: A controller is provided, operable to control a system on the basis of measurement data received from a plurality of sensors indicative of a state of the system, with at least partial autonomy, but in environments in which it is not possible to fully determine the state of the system on the basis of such sensor measurement data.

Abstract: An amplifier circuit controls the output current through an inductive load. A signal is amplified by one or more op amps, and sourced into a back to back coupling of an NPN transistor and a PNP transistor. In a positive circuit segment, current is sourced to an inductive load, and in a negative segment, current is sunk from the inductive load. The current at the output of the inductive load flows through a resistor, and the resultant voltage drop is negatively fed back to the op amp.

Abstract: A system and method for demultiplexing an RF signal including nested frequency division multiplexed (FDM) channels is disclosed. The system can demultiplex an RF signal including at least two nested sets of FDM channels extending over a bandwidth B.

Abstract: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.

Abstract: A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of “positive charge traps.” One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).

Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: A method for stacking chips within a multichip module package is disclosed. A first chip is bonded to a substrate. A passivation layer is then deposited on a top surface of the first chip. After a first adhesive layer has been deposited on top of the passivation layer, an interposer is placed on the adhesive layer. Next, a second adhesive layer is deposited on the interposer. Finally, a second chip is bonded to the interposer via the second adhesive layer.

Abstract: A process for selectively removing a silicon-containing material through use of a byproduct of a chemical vapor deposition is disclosed. The process includes fabricating an insulating film upon a silicon base layer such that the insulating film includes a cavity. A diffusion barrier layer is deposited into the cavity. The diffusion barrier layer is formed during a chemical vapor deposition which produces an alkyl halide as a byproduct. A photoresist layer is fabricated upon a silicon-containing material. A portion of the photoresist is removed, thereby exposing a portion of the silicon-containing material. The exposed portion of the silicon-containing material is removed with a chemical etch solution including the alkyl halide.

Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.

Abstract: An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a “floating voltage” which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout.

Abstract: A vehicle includes an arrangement, such as an internal-combustion engine coupled with a generator, for converting the energy in fuel into electrical form, while generating exhaust. An exhaust cleaning arrangement, such as a catalytic converter, preferably operating at a high temperature, cleanses the exhaust. During deceleration of the vehicle, excess electrical energy is used to heat the exhaust cleaning arrangement.

Abstract: A method is provided for correcting errors in position derived from an inertial measurement unit (IMU), by performing a first zero velocity update at a time when the IMU is at rest, recording the time and position of the IMU at a subsequent start of a period of interest after the first zero velocity update, recording the time and position of the IMU at the end of the period of interest, performing a second zero velocity update at the end of the period of interest with the IMU at rest, and then recording a velocity indicated from the IMU, and deriving an accumulated error in position from the recorded data, by approximating errors in velocity by a function of time with a parameter determined from the recorded indicated velocity, and integrating the function over the period of interest to determine the accumulated error in position during the period of interest.

Abstract: An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.