Abstract: The system and method of implementing a high reliability flash memory recorder comprising warm spare and error code correction bytes across several multi-chip modules. The use of redundant field programmable gate arrays and/or processors for command and control increases redundancy. The system and method has lookup table-based mechanisms combined with programming to determine when to substitute a warm spare byte as well as when to declare a block of memory as “bad” and no longer to be used. The system may use multiple memory banks with power switching per bank to reduce power consumption as well as increase reliability when the array is not being accessed.