Abstract: An apparatus and methods to fabricate the apparatus for balancing a string of N series-connected electrical energy units (such as battery cells or modules) comprising: a transformer with a magnetic core and N windings; N switch circuits; N driver circuits, each driver circuit operable to turn ON/OFF a respective switch circuit in a discharging or charging or idling configuration; and a controller circuit.

Abstract: A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit.

Abstract: An apparatus and methods to fabricate the apparatus for balancing a string of N series-connected electrical energy units (such as battery cells or modules) comprising: a transformer with a magnetic core and N windings; N switch circuits; N driver circuits, each driver circuit operable to turn ON/OFF a respective switch circuit in a charging or discharging or idling configuration; and a controller circuit.

Abstract: A driver for a power transistor switch comprising a FET complementary output stage which is driven by another FET complementary pre-driver stage which is further driven by an input-buffer and level-shifter stage. The pre-driver stage includes a current-limiting and cross-delaying circuit which is inserted in between drains terminals of a complementary FET pair. The current-limiting and cross-delaying circuit limits shoot-current at the pre-driver stage; and in conjunction with the FET pair and the input-buffer and level-shifter stage, it is adapted to delay turning on one complementary output FET until after the other complementary output FET is turned off, thereby preventing cross conduction at the output stage.