Abstract: An oscillator delay stage is described. The oscillator delay stage includes at least one differential input; a pair of single ended inverters for each differential input; and, a differential output. With respect to the pair of single ended inverters for each differential input, each pair of single ended inverters further include for their corresponding differential input: i) a first single ended inverter whose input is coupled to a + input of the corresponding differential input; and, ii) a second single ended inverter whose input is coupled to a ? input of the corresponding differential input. With respect to the differential output, the differential input further includes: i) a + output that is coupled to each said second single ended inverter output; ii) a ? output that is coupled to each said first single ended inverter output.

Abstract: A method is described that involves automatically generating a physical behavior curve from a process description; where, the process description describes a process. The method also involves automatically generating a device model for the process from the physical behavior curve; where, the device model is represented in geometric form. The method also involves attempting to automatically generate, with the device model and with a geometric optimization sequence, a circuit design for the process.

Abstract: A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved numerically with great efficiency. Prior work discloses the design of many different analog circuit cells such as operational amplifiers, spiral inductors, and LC oscillators which can be cast as geometric programs. The present disclosure adds to this layout floorplanning constraints in posynomial form that can be mixed with design constraints for different analog circuits. This allows the simultaneous design and floorplanning of numerous analog circuits using geometric programming. Thus, the design and floorplanning can be performed optimally in a single step.

Abstract: Methods are described that involve characterizing an oscillator's jitter or phase noise over a plurality of the oscillator's effective number of delay stages. The oscillator comprises a series of delay stages. Each one of the effective number of delay stages, if selected for the oscillator, describes a respective permissible range of inverter drive strengths that may be used within each delay stage of the oscillator to achieve a respective jitter or phase noise characteristic.

Abstract: A power distribution circuit built with wiring layers that reside above an analog circuit is described. The power distribution circuit comprises one or more capacitive structures that reside above the analog circuit. At least one of the one or more capacitive structures has electrodes that provide supply and/or reference voltages and their corresponding currents to said analog circuit. A machine readable medium is described to perform a method in order to design the power distribution circuit. The method includes: assigning a specific supply or reference voltage to each of the electrodes; and, determining wiring dimensions for each of the electrodes. The wiring dimensions for the electrodes of at least one of the capacitive structures is are based at least in part on IR drop concerns.

Abstract: A capacitive structure is described that comprises a first node and a second node. The first node comprises a first pair of vertically aligned strips that are electrically connected with one or more vias and a second pair of vertically aligned strips that are electrically connected with one or more vias. The higher strips of both of the pairs are at a same metal level and the lower strips of both of the pairs are at a same lower metal level. The second node comprises, at the metal level, a first metal structure having a pair of windows. A first of the windows surround and are isolated from a first of the higher strips. A second of the windows surround and are isolated from a second of the higher strips. The second node also comprises, at the lower metal level, a second metal structure having a pair of windows. A first of the windows surround and are isolated from a first of the lower strips. A second of the windows surround and are isolated from a second of the lower strips.

Abstract: A method is described that involves recognizing that a variable within a monomial or posynomial expression for a characteristic of an analog or mixed signal system has a dependency on a lower level expression. Then, retrieving from a database the lower level expression and substituting it into the expression in place of the variable so as to describe the system at a greater level of detail than the variable did.

Abstract: A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.

Abstract: In one embodiment, the invention is a method. The method is a method of routing a circuit having a set of nets and a set of circuit elements specified as a slicing tree and a set of linear constraints. The method includes finding short paths for the set of nets based on a minimum-spanning-tree solution to a floorplan derived from the slicing tree for each net of the set of nets. The method also includes routing the nets as conductors within channels of the floorplan, the conductors having locations satisfying a set of linear constraints based on the solution of a linear optimization problem.

Abstract: A method for providing a convex piecewise-linear expression which can be used for a system having thousands of variables is described. Data regions are defined and planes fitted to the data with the limitation that no plane exceeds the data by more than a set tolerance. A set of planes is formed and planes are added to the set one at a time found on the amount error reduction. After a plane is added to the set refitting occurs and another plane is selected for inclusion into the set.

Abstract: A method is described that involves automatically laying out a circuit structure in software by describing in a software environment the placement of a gate structure relative to a diffusion region. The gate structure has: 1) a pair of gate fingers that project over the diffusion region along a y axis; and, 2) a landing area for receiving multiple contacts from a metal 1 layer. The method also involves running a pair of source fingers at a metal 1 layer over the diffusion area and along the y axis. The pair of source fingers are outside the pair of gate fingers and are an extension of a metal 1 source wire running along an x axis. The method also involves placing a metal 1 gate pad layer over the landing area.

Abstract: A method is described that involves retrieving a generic layout description of a circuit structure from a first database that stores a plurality of generic layout descriptions. The method also involves retrieving a foundry design rule profile of a semiconductor manufacturing process from a second database that stores a plurality of semiconductor manufacturing process design rule profiles.