Abstract: The present disclosure relates to a device for controlling the access to a cache structure comprising multiple cache sets during the execution of at least one computer program, the device comprising a module for generating seed values during the execution of the at least one computer program; a parametric hash function module for generating a cache set identifier to access the cache structure, the identifier being generated by combining a seed value generated by the module for generating seed values and predetermined bits of an address to access a main memory associated to the cache structure.

Abstract: Mechanisms are provided for optimizing irregular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which irregular memory references access a storage of a software cache of a data processing system through a transactional cache mechanism of the software cache.