Patents Assigned to Barcelona Supercomputing Center—Centro Nacional de Supercomputacion
  • Patent number: 11907765
    Abstract: Fog computing systems are provided comprising edge-nodes and middle-nodes between edge-nodes and cloud-node. These nodes form a hierarchical structure with each cloud, middle node having children nodes, and each middle, edge node having a parent-node. Each edge-node receives data from sensors, assigns reception-timestamp to each data indicating when data has been received to produce series of timestamp-ordered data, trains local model through machine-learning based on said series of timestamp-ordered data, and sends said series to parent-node of the edge-node. Each middle-node collects series of timestamp-ordered data from children nodes of the middle-node, trains supra-local model through machine-learning based on said collected series of timestamp-ordered data, and sends said collected series to parent-node of the middle-node. Parent-children structures, edge-nodes and middle-nodes for such fog computing systems are also provided.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 20, 2024
    Assignees: BARCELONA SUPERCOMPUTING CENTER—CENTRO NACIONAL DE SUPERCOMPUTACIÓN, UNIVERSITAT POLITÈCNICA DE CATALUNYA
    Inventors: Juan Luís Pérez Rico, Alberto Gutiérrez Torre, Josep Lluís Berral García, David Carrera Perez
  • Patent number: 11474988
    Abstract: Methods are provided of optimizing a tree-structured distributed-index with tree-nodes including data-elements and parent-child relations between tree-nodes. The distributed-index is stored in distributed system including computer-nodes each storing tree-nodes and a tree-map structurally describing the distributed-index. The methods include: inspecting the tree-map in first computer-node to determine whether the distributed-index is imbalanced due to a first tree-node in first computer-node and, in said case: notifying to other computer-nodes that first tree-node is replicable, to provoke that any request from other computer-nodes of inserting a data-element in first-tree-node includes inserting the data-element in corresponding child-node of first-tree-node; and verifying whether the other computer-nodes have been notified and, in said case, replicating data-elements stored in first tree-node into children-nodes thereof.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 18, 2022
    Assignees: BARCELONA SUPERCOMPUTING CENTER—CENTRO NACIONAL DE SUPERCOMPUTACIÓN, UNIVERSITAT POLITÉCNICA DE CATALUNYA
    Inventors: Cesare Cugnasco, Yolanda Becerra Fontal
  • Patent number: 11436048
    Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: September 6, 2022
    Assignees: Barcelona Supercomputing Center—Centro Nacional De Supercomputacion, Universitat Politecnica De Catalunya
    Inventors: Xubin Tan, Carlos Alvarez Martinez, Jaume Bosch Pons, Daniel Jimenez Gonzalez, Mateo Valero Cortes
  • Patent number: 10282203
    Abstract: Methods and devices for discovering multiple instances of recurring values within a vector are disclosed. A first method calculates the prior instances of the vector. A second method calculates the last unique instances of the vector. An implementation of these methods as SIMD instructions is proposed. Sequential and parallel CAM implementations are also disclosed. The proposed methods can be used to correct conflicting indexes in vector memory indexed operations. Furthermore, an application to a vectorized sorting algorithm is proposed.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: May 7, 2019
    Assignee: BARCELONA SUPERCOMPUTING CENTER—CENTRO NACIONAL DE SUPERCOMPUTACIÓN
    Inventors: Timothy Hayes, Oscar Palomar Pérez, Osman Unsal, Adrian Cristal Kestelman, Mateo Valero Cortés
  • Patent number: 8527974
    Abstract: Mechanisms are provided for optimizing regular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which regular memory references access a storage of a software cache of a data processing system through a high locality cache mechanism of the software cache.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: September 3, 2013
    Assignees: International Business Machines Corporation, Barcelona Supercomputing Center—Centro Nacional de Supercomputacion
    Inventors: Eduard Ayguade, Tong Chen, Alexandre E. Eichenberger, Marc Gonzalez Tallada, Xavier Martorell, John K. O'Brien, Kathryn M. O'Brien, Zehra N. Sura, Tao Zhang