Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Abstract: A mesh network architecture is disclosed whose protected services can be restored quickly after the failure of a network element (i.e., a network node, a network transmission facility). Furthermore, the protected services can be restored after all single and most multiple network-element failures as quickly as a ring network can recover from a single network-element failure. And still furthermore, the illustrative embodiment is also advantageous in that it can be administered and maintained, for most purposes, as a collection of distinct ring networks. Embodiments of the present invention can use any protocol or transmission technology (e.g., wavelength division multiplexing, SONET/SDH, ATM, etc.). Furthermore, embodiments of the present invention distinguish between the transport function, the provisioning function, and the fault notification functions of a network and provide that each of the functions can be accomplished by different networks using different protocols.

Abstract: A system and method for regenerating a client clock signal for use in optical communications is disclosed. The system and method involves using a carrier clock signal and a client clock signal to calculate quantities of data that are received and transmitted at an edge node and then adjusting a clock source in response to the difference between the calculated quantities of received and transmitted data.

Abstract: A hardware-based technique for policing traffic in a network node involves programming a set of algorithm-specific policing primitives that establishes a relationship between condition primitives and action primitives and populating a searchable memory with a set of indexed action primitives. Action primitives are then selected from the searchable memory in response to condition primitives related to a received datagram. Policing actions related to the datagram are performed in response to the action primitive. Because the algorithm-specific policing primitives are programmable, a network node can be adapted to implement a wide variety of policing algorithms. Additionally, multiple different policing algorithms can be implemented in hardware without the need for a different set of combinational logic for each different policing algorithm.

Abstract: A network processor IC for processing network traffic includes a bus interface and a software programmable search engine communications module. The bus interface of the network processor IC is not specific to a particular search engine and the software programmable search engine communications module enables communications to be conducted between the network processor IC and the search engine via the bus interface according to whatever communications protocol the search engine requires. Using the software programmable search engine communications module, a network processor IC is software programmed to communicate with a particular search engine in a manner that is completely compatible with the search engine.

Abstract: A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.

Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Abstract: A method of coherently provisioning one or more paths through a transport network is disclosed. In other words, none of the traffic paths are provisioned unless all of the traffic paths can be provisioned. All of the nodes in one or more transport networks are listed that must be configured to provision all of the proposed traffic paths, and all of the nodes are checked, one after another, to ensure that each node can, in fact, provide all of the resources needed to establish all of the proposed traffic paths before any of the traffic paths are actually provisioned. As each node is visited, the set-up message directs each node to reserve, but not actually provision, the resources to be provided by that node for all of the proposed traffic paths. When all of the nodes have been visited, the set-up message re-visits each node and directs each node to actually provision the resources that had been previously reserved.

Abstract: A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.

Abstract: A telecommunications switching node comprising a plurality of input and output (I/O) ports configured to receive and transmit telecommunications signals, a switching core comprising a plurality of switching networks and a backplane connecting each of the plurality of I/O ports to each of the switching networks in the switching core. A non-blocking path is provided for each communications signal from any of the input ports to any of the output ports via one of the switching networks in the switching core. Further, the switching system effects a non-blocking path via all of the switching networks in the switching core. Advantageously, the switching core comprises a pair of switching networks. Further, this telecommunications switching node is expandable by adding a second switching core comprising a pair of switching networks to the node. One or more of the plurality of I/O ports may include a switching network to effect connection through the backplane to both pairs of switching networks.

Abstract: A novel multiport overhead cell processor for processing overhead cells (e.g., SONET/SDH overhead bytes, etc.) in a telecommunications node is disclosed. Some embodiments of the present invention advantageously employ a single instance of logic to process overhead cells for all of a node's input ports. The illustrative embodiment comprises a single overhead cell processor and a memory for storing instances of state variables associated with each input port.

Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Abstract: A telecommunications node architecture is disclosed that comprises multiple switching units that are connected to transceiver banks in a novel topology to enhance the reliability of the telecommunications network. Furthermore, the architecture of the illustrative embodiment facilitates redundancy in a high-bandwidth add/drop multiplexor environment.

Abstract: A method of the grooming traffic signals through a composite switch is disclosed that enables a traffic signal that is being transmitted between any two constituent switches to be re-routed through the composite switch without a hit (i.e., the dropping, replacing, inserting, or repeating of at least one bit in the traffic signal). This applies whether the constituent switches are adjacent in the composite switch or not. The composite switch in accordance with the illustrative embodiment comprises multiple routes between adjacent constituent switches and incorporates a mechanism that compensates for differential propagation delays along the routes. And still furthermore, the composite switch in accordance with the illustrative embodiment comprises alternative routes through different constituent switches and incorporates a mechanism that compensates for differential propagation delays through the constituent switches.

Abstract: A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.

Abstract: A telecommunications network node architecture is disclosed that enables a telecommunications network that uses automatic protection switching to be expanded to include more nodes than its standard protocol provides for without modifying the standard protocol or the existing nodes in the network. Although the illustrative embodiment is depicted as using the SONET/SDH protocol, it will be clear to those skilled in the art, after reading this specification, how to make and use embodiments of the present invention that use automatic protection switching with another protocol. The illustrative embodiment comprises: an automatic protection switching channel that defines an address space in the telecommunications network; a node that is uniquely identified by an address in the address space; and a node that is not uniquely identified by an address in the address space.

Abstract: A SONET/SDH architecture is disclosed that enables the multiplexing of STS-1's from different SONET/SDH rings into a single STS-N for transmission via a single optical fiber, but while maintaining the association of each of the STS-1's with its respective SONET/SDH ring. For example, when an STS-48 carries 12 STS-1's from a first SONET/SDH ring and 12 STS-1's from a second SONET/SDH ring, the STS-48 carries: the automatic protection switching channel for the 12 STS-1's from the first SONET/SDH ring (with addresses specified in the address space of the first SONET/SDH ring); and the automatic protection switching channel for the 12 STS-1's from the second SONET/SDH ring (with addresses specified in the address space of the second SONET/SDH ring).

Abstract: A telecommunications node architecture is disclosed that facilitates the loop-back of a signal in an add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: An apparatus and method that extend the automatic protection switching protocol to address at least 256 network nodes. By using overhead bytes as extended APS node IDs, large single ring SONET/SDH systems can be avoided. This means APS messages that force every node into a single ring can be avoided and recovery performance from a break in the ring or a node fault can be improved. The protocol for the extended automatic protection switching channels takes multiple extended APS node IDs from tributary lines and merges those extended APS ID's into a single SONET/SDH stream on another line. Placement of the extended APS node ID's in the overhead bytes of SONET/SDH frames allows easy relay around each SONET/SDH ring.

Abstract: A composite add/drop multiplexor architecture is disclosed that facilitates the loop-back of a signal in a composite add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.