Patents Assigned to Bay Microsystems, Inc.
  • Publication number: 20150334034
    Abstract: Systems and methods accessing remote digital data over a wide area network (WAN) are disclosed. In an embodiment, a network device is disclosed. The network device includes a local area network (LAN) switching fabric physical interface configured to communicate according to a LAN switching fabric protocol, a WAN physical interface configured to communicate according to a WAN protocol, and a fabric extension function configured to map LAN switching fabric interfaces to pseudo-ports, map pseudo-ports to WAN interfaces, and transmit LAN fabric datagrams received at the LAN switching fabric physical interface from the WAN physical interface via a mapped pseudo-port and a corresponding WAN interface.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 19, 2015
    Applicant: BAY MICROSYSTEMS, INC.
    Inventors: Robert Smedley, Soochon Radee, Suresh Shelvapille, Edward Kinzler, Richard Smedley, Joseph Senesi, Daniel Eigenbrode, John Wolf, Anunoy Ghosh, Gerard Jankauskas, Man Dieu Trinh
  • Patent number: 8861344
    Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: October 14, 2014
    Assignee: Bay Microsystems, Inc.
    Inventors: Man D. Trinh, Ryzsard Bleszynski, Barry T. Lee, Steve C. Chen, Eric K. Yang, Simon S. Chong, Tony J. Chiang, Jun-Wen Tsong, Goichiro Ono, Charles F. Gershman
  • Patent number: 8625411
    Abstract: A mesh network architecture is disclosed whose protected services can be restored quickly after the failure of a network element (i.e., a network node, a network transmission facility). Furthermore, the protected services can be restored after all single and most multiple network-element failures as quickly as a ring network can recover from a single network-element failure. And still furthermore, the illustrative embodiment is also advantageous in that it can be administered and maintained, for most purposes, as a collection of distinct ring networks. Embodiments of the present invention can use any protocol or transmission technology (e.g., wavelength division multiplexing, SONET/SDH, ATM, etc.). Furthermore, embodiments of the present invention distinguish between the transport function, the provisioning function, and the fault notification functions of a network and provide that each of the functions can be accomplished by different networks using different protocols.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 7, 2014
    Assignee: Bay Microsystems, Inc.
    Inventors: Santhanam Srivivasan, Sasisekharan Raguram, Pradeep Shrikrishna Limaye
  • Patent number: 8437641
    Abstract: A system and method for regenerating a client clock signal for use in optical communications is disclosed. The system and method involves using a carrier clock signal and a client clock signal to calculate quantities of data that are received and transmitted at an edge node and then adjusting a clock source in response to the difference between the calculated quantities of received and transmitted data.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: May 7, 2013
    Assignee: Bay Microsystems, Inc.
    Inventors: Barry Tsai Lung Lee, Chu-Jyh Chang, Goichoro Ono
  • Publication number: 20110314473
    Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifics the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.
    Type: Application
    Filed: August 29, 2011
    Publication date: December 22, 2011
    Applicant: BAY MICROSYSTEMS, INC.
    Inventors: Eric Kuo-Uei Yang, Jun-Wen Tsong
  • Patent number: 7957311
    Abstract: A hardware-based technique for policing traffic in a network node involves programming a set of algorithm-specific policing primitives that establishes a relationship between condition primitives and action primitives and populating a searchable memory with a set of indexed action primitives. Action primitives are then selected from the searchable memory in response to condition primitives related to a received datagram. Policing actions related to the datagram are performed in response to the action primitive. Because the algorithm-specific policing primitives are programmable, a network node can be adapted to implement a wide variety of policing algorithms. Additionally, multiple different policing algorithms can be implemented in hardware without the need for a different set of combinational logic for each different policing algorithm.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: June 7, 2011
    Assignee: Bay Microsystems, Inc.
    Inventors: Man Trinh, Goichiro Ono, Yihui Wu
  • Patent number: 7822877
    Abstract: A network processor IC for processing network traffic includes a bus interface and a software programmable search engine communications module. The bus interface of the network processor IC is not specific to a particular search engine and the software programmable search engine communications module enables communications to be conducted between the network processor IC and the search engine via the bus interface according to whatever communications protocol the search engine requires. Using the software programmable search engine communications module, a network processor IC is software programmed to communicate with a particular search engine in a manner that is completely compatible with the search engine.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: October 26, 2010
    Assignee: Bay Microsystems, Inc.
    Inventors: Simon Chong, Steven Pan
  • Publication number: 20100254387
    Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 7, 2010
    Applicant: BAY MICROSYSTEMS, INC.
    Inventors: Man D. Trinh, Ryzsard Bleszynski, Barry T. Lee, Steve C. Chen, Eric K. Yang, Simon S. Chong, Tony J. Chiang, Jun-Wen Tsong, Goichiro Ono, Charles F. Gershman
  • Patent number: 7742405
    Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: June 22, 2010
    Assignee: Bay Microsystems, Inc.
    Inventors: Man D. Trinh, Ryzsard Bleszynski, Barry T. Lee, Steve C. Chen, Eric K. Yang, Simon S. Chong, Tony J. Chiang, Jun-Wen Tsong, Goichiro Ono, Charles F. Gershman
  • Patent number: 7742411
    Abstract: A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: June 22, 2010
    Assignee: Bay Microsystems, Inc.
    Inventors: Man Trinh, Steve Chen, Martin Chang, Ray Chen
  • Publication number: 20100098432
    Abstract: A system and method for regenerating a client clock signal for use in optical communications is disclosed. The system and method involves using a carrier clock signal and a client clock signal to calculate quantities of data that are received and transmitted at an edge node and then adjusting a clock source in response to the difference between the calculated quantities of received and transmitted data.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 22, 2010
    Applicant: BAY MICROSYSTEMS, INC.
    Inventors: Goichoro Ono, Barry Tsai Lung Lee, Chu-Jyh Chang
  • Patent number: 7433964
    Abstract: A method of coherently provisioning one or more paths through a transport network is disclosed. In other words, none of the traffic paths are provisioned unless all of the traffic paths can be provisioned. All of the nodes in one or more transport networks are listed that must be configured to provision all of the proposed traffic paths, and all of the nodes are checked, one after another, to ensure that each node can, in fact, provide all of the resources needed to establish all of the proposed traffic paths before any of the traffic paths are actually provisioned. As each node is visited, the set-up message directs each node to reserve, but not actually provision, the resources to be provided by that node for all of the proposed traffic paths. When all of the nodes have been visited, the set-up message re-visits each node and directs each node to actually provision the resources that had been previously reserved.
    Type: Grant
    Filed: January 20, 2002
    Date of Patent: October 7, 2008
    Assignee: Bay Microsystems, Inc.
    Inventors: Sasisekharan Raguram, Santhanam Srinivasan
  • Patent number: 7349435
    Abstract: A novel multiport overhead cell processor for processing overhead cells (e.g., SONET/SDH overhead bytes, etc.) in a telecommunications node is disclosed. Some embodiments of the present invention advantageously employ a single instance of logic to process overhead cells for all of a node's input ports. The illustrative embodiment comprises a single overhead cell processor and a memory for storing instances of state variables associated with each input port.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: March 25, 2008
    Assignee: Bay Microsystems, Inc.
    Inventor: Peter J Giacomini
  • Patent number: 7349411
    Abstract: A telecommunications switching node comprising a plurality of input and output (I/O) ports configured to receive and transmit telecommunications signals, a switching core comprising a plurality of switching networks and a backplane connecting each of the plurality of I/O ports to each of the switching networks in the switching core. A non-blocking path is provided for each communications signal from any of the input ports to any of the output ports via one of the switching networks in the switching core. Further, the switching system effects a non-blocking path via all of the switching networks in the switching core. Advantageously, the switching core comprises a pair of switching networks. Further, this telecommunications switching node is expandable by adding a second switching core comprising a pair of switching networks to the node. One or more of the plurality of I/O ports may include a switching network to effect connection through the backplane to both pairs of switching networks.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: March 25, 2008
    Assignee: Bay Microsystems, Inc.
    Inventor: Walter Michael Pitio
  • Patent number: 7349403
    Abstract: A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: March 25, 2008
    Assignee: Bay Microsystems, Inc.
    Inventors: Barry Lee, Man Dieu Trinh
  • Patent number: 7310348
    Abstract: A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: December 18, 2007
    Assignee: Bay Microsystems, Inc.
    Inventors: Man D. Trinh, Ryzsard Bleszynski, Barry T. Lee, Steve C. Chen, Eric K. Yang, Simon S. Chong, Tony J. Chiang, Jun-Wen Tsong, Goichiro Ono, Charles F. Gershman
  • Patent number: 7269130
    Abstract: A telecommunications node architecture is disclosed that comprises multiple switching units that are connected to transceiver banks in a novel topology to enhance the reliability of the telecommunications network. Furthermore, the architecture of the illustrative embodiment facilitates redundancy in a high-bandwidth add/drop multiplexor environment.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: September 11, 2007
    Assignee: Bay Microsystems, Inc.
    Inventor: Walter Michael Pitio
  • Patent number: 7224706
    Abstract: A method of the grooming traffic signals through a composite switch is disclosed that enables a traffic signal that is being transmitted between any two constituent switches to be re-routed through the composite switch without a hit (i.e., the dropping, replacing, inserting, or repeating of at least one bit in the traffic signal). This applies whether the constituent switches are adjacent in the composite switch or not. The composite switch in accordance with the illustrative embodiment comprises multiple routes between adjacent constituent switches and incorporates a mechanism that compensates for differential propagation delays along the routes. And still furthermore, the composite switch in accordance with the illustrative embodiment comprises alternative routes through different constituent switches and incorporates a mechanism that compensates for differential propagation delays through the constituent switches.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: May 29, 2007
    Assignee: Bay Microsystems, Inc.
    Inventor: Christoph Dominique Loeffler-Lejeune
  • Patent number: 7221687
    Abstract: A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: May 22, 2007
    Assignee: Bay Microsystems, Inc.
    Inventor: Donald David Shugard
  • Patent number: 7173902
    Abstract: A telecommunications network node architecture is disclosed that enables a telecommunications network that uses automatic protection switching to be expanded to include more nodes than its standard protocol provides for without modifying the standard protocol or the existing nodes in the network. Although the illustrative embodiment is depicted as using the SONET/SDH protocol, it will be clear to those skilled in the art, after reading this specification, how to make and use embodiments of the present invention that use automatic protection switching with another protocol. The illustrative embodiment comprises: an automatic protection switching channel that defines an address space in the telecommunications network; a node that is uniquely identified by an address in the address space; and a node that is not uniquely identified by an address in the address space.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: February 6, 2007
    Assignee: Bay Microsystems, Inc.
    Inventors: Piers John Daniell, Heena Nandu, Srinivasan Murari