Abstract: A computer implemented method for searching for a key in a radix search tree in a memory of a computer system. A table of keys is organized in a radix search tree stored in a memory of a computer system. The keys are divided into a string of symbols. Each node in the tree corresponds to a symbol. A path from a root node to a leaf node at level n in the tree represents a string of n symbols comprising a key. Each node is capable of having m possible entries corresponding to m possible symbol values. Each entry comprises a pointer to a son node and an existence map indicating which entries exist in the son node. In the preferred embodiment, the existence map is a bit mask that indicates, based on bit positions enabled and disabled in the bit mask, which entries exist in the son node pointed to by the pointer. By providing an existence map along with the pointer to a son node, m memory locations for m entries are allocated for the son node only if all of the m possible entries are used.

Abstract: A system for managing virtual circuits and determining proper routing of packets in a network environment. The network includes a connection-oriented subnetwork and an arrangement of routers coupled to the connection-oriented subnetwork. The system determines paths to each exit router by considering all possible paths through the connection-oriented subnetwork. The system also determines paths to each exit router by considering existing virutal circuits through the connection-oriented subnetwork. Finally, the system determines and establishes a most beneficial new virtual circuit for the network. Additionally, the rate at which new virtual circuits are established may be regulated by the system.

Abstract: The switch fabric of the ATM switch, i.e., the ATM switch backplane bus, switches a cell based on routing information provided by the source LAN or ATM module to an output port on a destination LAN or ATM module of the switching hub. In the described system, the ATM switch is preconfigured to provide a fully connected topology between ports of all modules. In one embodiment, ATM cells transmitted across the ATM switch fabric between a source LAN or ATM module and a destination LAN module, e.g., Token Ring, FDDI or Ethernet, is accomplished by way of a routing tag prepended on the ATM cells. The routing tag provides both unicast and multicast group destination information such that the ATM cells are routed to the appropriate port on a given destination module without the need to establish a virtual circuit between the source module and the destination module using VPI/VCIs.

Abstract: A method for determining the topology of a mixed-media network is provided. According to the method, the network is divided into communities of devices that support a common topology mechanism ("spheres"). On each sphere, one or more sphere topology agents generate and accumulate topology data for the devices on the sphere using the topology mechanism that is supported by the devices within the sphere. A global topology agent collects the topology data for each sphere from the various sphere agents and assembles the data to determine the global topology of the mixed-media network. The global topology agent begins by collecting data from a current sphere and identifies additional spheres based on data stored in boundary devices within the current sphere. The global topology agent then repeats the same process with the additional spheres until topology data has been collected from all of the spheres in the mixed-media network.

Abstract: A multitasking computer system having multiple parallel and independently executing processors. Each processor has multiple pipeline stages. Each stage in the pipeline can be simultaneously executing a process. More processes than the sum of pipeline stages for all processors exist at any given time, which allows processes to migrate between processors and allows the processes queued at any one processor to increase, i.e., back up, momentarily without causing other processors to sit idle. Related to the ability to support at least as many processes as there are the sum of pipeline stages in all of the processors is the ability of the preferred embodiment of the present invention to migrate processes between processors. When a processor completes execution of an instruction for a particular process, the program counter for the process is incremented to point to the next instruction in the process. The process is then requeued by a scheduler.

Abstract: A method for filtering an internetwork packet wherein multiple paths to a destination network are provided. The method comprises the step of providing a forwarding list that comprises a plurality of entries selected by a user. The forwarding list indicates a plurality of possible paths to a selected destination. One of the entries is selected by the user as a primary entry that indicates a default path. When an internetwork packet is destined for the destination network is received, the packet is forwarded to the destination network via the default path if the primary entry indicates a valid path. Otherwise, the packet is forwarded to the destination network via another path as indicated by another entry. According to an alternative embodiment, a different forwarding list is provided for each subnetwork of a source network, and the forwarding list is selected based on the source address of the packet.

Abstract: A pipeline processor having an add circuit configured to execute separate atomic add instructions in consecutive clock cycles, wherein each separate atomic add instructions can be updating the same memory address location. In one embodiment, the add circuit includes a carry-save-add circuit coupled to a set of carry propagate adder circuits. The carry-save-add circuit is configured to perform an add operation in one processor clock cycle and the set of carry propagate adder circuits are configured to propagate, in subsequent clock cycles, a carry generated by the carry-save-add circuit. The add circuit is further configured to feedforward partially propagated sums to the carry-save-add circuit as at least one operand for subsequent atomic add instructions. In one embodiment, the pipeline processor is implemented on a multitasking computer system architecture supporting multiple independent processors dedicated to processing data packets.

Abstract: A method and apparatus for generating a display containing information about both the local and remote traffic handled by an integrated router/hub is provided. An integrated router/hub routes local messages between devices on a first local area network, and routes remote messages between the first local area network and a second local area network. The integrated router/hub stores a first set of values related to the local messages, and a second set of values related to the remote messages. A network management station executes a network management application the includes instructions which cause the network management station to generate a display of the information stored in the integrated router/hub. In response to user input, the network management station requests the information from the integrated router/hub, receives the information from the integrated router/hub, and generates the display of the information. The display may include charts that illustrate statistics derived from the information.

Abstract: A method and apparatus for a node to automatically switch between half-duplex and full-duplex transmission in CSMA/CD networks characterized by a first and second device coupled over a communication link to allow communication of information and control signals between the first and second device. Each of the two devices include a transmit circuit and a receive circuit, wherein the first device begins to transmit information on a first communication circuit, the first communication circuit providing for communication of information between the first device and the second device, and the second device receives the transmitted information.

Abstract: An apparatus which provides the user with an indication of the computer network's health. The indication is provided by a network management station on the computer network. The network management station has a distributable piece of code which instructs agents to gather diagnostic and status information. The network management station then evaluates the network specific diagnostic and status data gathered by the agents. Based on the evaluation, the network management station generates a representation of the computer network's functionality (i.e., its "health"). Thereby, the user can readily determine whether the computer network requires repairs.

Abstract: In a segmentation and reassembly module in a local area network switch module, a method and apparatus for storing fixed length data cells received from an ATM network in a plurality of memory buffers during the reassembly of the data cells in to a variable length data packet to be transmitted on an attached local area network.

Abstract: A method and apparatus are provided for grouping the network entities that belong to a network system into logical groups, and generating a display of the network based on the logical groups. In the highest level display, a single visual indicator, such as an icon, is used to represent each logical group. Thus, a display of the entire network system need only contain as many visual indicators as there are logical groups. Typically, the number of logical groups will be significantly less than the number of actual network resources. Consequently, entire large network systems may be displayed without crowding the display screen with small, difficult to read icons. The logical groups are formed based on the type of connections that exist between the various logical entities in the network. Site groups are formed by combining all local area network connections that connection common network entities. Region groups are formed by combining all wide area network connections that connect common network entities.

Abstract: A method of configuring a network. The network includes some physical devices, some hosts, and a network management tool. The method comprises the following steps. First, generate a set of leaf nodes. Each leaf node includes at least one physical device and connects to at least one host. Next, generate an adjacency matrix from said set of leaf nodes. Next, generate a set of interconnect nodes, the interconnect nodes connect the set of leaf nodes. Next, determine the resource availability for the set of interconnect nodes. Finally, configure the set of interconnect nodes and the set of leaf nodes after determining that sufficient resources are available.

Abstract: A token ring network having virtual token rings comprised of one or more physical token rings. A media access control (MAC) layer device such as a bridge or switching hub has at least two ports assigned the same ring number such that token ring segments connected to the ports operate as though on the same physical token ring segment even though they are electrically isolated. All physical rings in the same virtual ring are considered to be in the same broadcast domain.

Abstract: It is desirable to be able to automatically map the topology of a computer network. To automatically map the topology of a computer network, a new method is proposed. First, all the network management modules (NMMs) in the network start off broadcasting multicast packets informing other units of their presence. When a network management module detects that only a single unit is connected to a particular slot-port combination, then that network management module designates the single unit as being a downstream unit in a network topology table. After updating its network topology table, the network management module sends a quench packet to the single unit to silence the downstream unit. These steps are repeated for all occurrences of a single unit connected to a particular slot-port combination in that network. After this occurs, the very bottom layer of the network has been detected and it's topology has been mapped.

Abstract: A method and apparatus for filtering data packets from a network device, such as a LAN switch, onto a network coupled thereto based on the content of the data packets. A pattern is defined and a forwarding action performed on data packets whose contents match or do not match the pattern, according to a specified condition. Filters may be configured on a per port basis, i.e., a filter can be applied to data packets entering or exiting a specific port on a networking device such as a LAN switch. A data packet received or transmitted at a port of a network device whose contents meet a condition specified by a filter may be processed in a number of ways: the packet may be forwarded to a normal destination port according to normal forwarding rules, forwarded to additional destination ports, forwarded to a monitor destination port, dropped, or subjected to another filter. The next filter may define a different forwarding action for data packets that do not meet the condition specified by the present filter.

Abstract: Editing the parameters for several network devices coupled to a computer network can be a cumbersome task. To simplify the task, a method of editing parameter settings for more than one network device using a graphical user interface is introduced. First, a set of network devices is displayed on a display screen. Then, a user selects a set of network devices to edit parameters for. Next, a list of parameters for the selected network devices is displayed on a display screen. The parameters that have the same value for all the selected network devices are displayed on the screen. However, parameters that do not have the same value for all the selected network devices are not displayed on the screen. Instead, the field is usually left blank. A user can edit the parameter settings displayed on the screen. When a parameter modification is approved, the modified parameter value is sent to all the selected network devices.

Abstract: A method for searching for keys of arbitrary width in a table in a memory of a computer system by repeatedly executing lookup instructions on a lookup processor. The lookup processor executes a lookup instruction to find a key in a table. The execution of the lookup instruction results in a key being found, or a key not being found. If the key is not found, the process is requeued by a scheduler with the program counter register for the process pointing to the instruction immediately following the lookup instruction, i.e., the next instruction. In the event the key is found in the table, the entry in the table associated with the key contains the memory address of the next instruction to be executed. This memory address is loaded into the program counter register associated with the process in which the lookup instruction was executed. The scheduler requeues the process, later dequeues it, and the instruction pointed to by the program counter register is fetched by an instruction fetch unit.

Abstract: Heavily relied upon network devices require backup power systems. To efficiently allocate power, a highly programmable backup power system is desired. The present invention discloses a redundant power supply unit that provides backup power to network devices. The redundant power supply unit will supply power to the network devices in the case that their local internal power supplies fail. Furthermore, if there is a power outage from the utility company, the redundant power supply will supply power to the network devices from a internal battery pack. When the internal battery pack is engaged, the redundant power supply uses programmed control logic that controls how the power from internal battery pack will be allocated. Specifically, since the power from the batteries is limited, it can be used to power some network devices for a certain amount of time and other network devices for a longer amount of time.

Abstract: A method for handling cache misses in a computer system. A prefetch unit fetches an instruction for execution by one of a plurality of coprocessors. When the preferred embodiment of the present invention experiences a cache miss in a prefetch unit, the process for which an instruction is being fetched is passed off to a memory processor which executes a read of the missing cache line in memory. While the process is executing in memory processor, or queued by the scheduler for execution of the same instruction, the prefetch unit continues to dispatch other processes from the its queue to the other processors. Thus, the computer system, including the processors, do not stall. Processors continue to execute processes. The prefetch unit continues to dispatch processes. When the memory read is completed, the process in which the cache miss occurred is rescheduled by the scheduler. The prefetch again attempts to fetch and decode the instruction and arguments.