Abstract: System and method for generating a Network on Chip (NoC) includes intaking a specification, where the specification includes, for each sub-NoC design, hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations thereof. Further, for each of the CSR controller in the sub-NoC, the sub-NoC design includes a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers and ingress and egress points of a boundary of the each sub-NoC. The network definition is generated for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points. NoCs may be generated based on the network definitions.
Type:
Grant
Filed:
January 7, 2025
Date of Patent:
June 2, 2026
Assignee:
BAYA SYSTEMS, INC.
Inventors:
Honnahuggi Harinath Venkata Naga Ambica Prasad, Narayana Sri Harsha Gade, Eric Norige
Abstract: A Network on Chip (NoC) includes a plurality of shared buffers configured to manage arriving flits with a plurality of logical queues, each of the plurality of logical queues configured to manage the arriving flits according to a virtual channel of an input port associated with the arriving flits and an output port corresponding to the arriving flits. A first set of arbitration logic is configured to output arbitration of flits from the plurality of logical queues to a second set of arbitration logic. The second set of arbitration logic is configured to arbitrate output flits from the first set of arbitration logic to the output port. Additionally, the configuration of the shared buffers with two-set of arbitration logic provides efficient arbitration of data transmission.
Type:
Application
Filed:
October 28, 2024
Publication date:
April 30, 2026
Applicant:
Baya Systems, Inc.
Inventors:
Joji PHILIP, Eric NORIGE, Jatinkumar Vithalbhai FULTARIA
Abstract: A method for load balancing flows of a Network on Chip (NoC) having a plurality of routers and a plurality of bridges arranged into a plurality of clusters described herein includes receiving packets at the NoC, the packet being associated with a target destination as specified by a cluster identifier and a local identifier. For receipt of each packet, the method includes routing the packet to a destination in the NoC according to the local identifier for the NoC having a same cluster identifier as the cluster identifier associated with the packet, and routing the packet according to a route lookup from referencing the cluster identifier and a path identifier associated with the packet for the NoC having a different cluster identifier from the cluster identifier associated with the packet.
Type:
Grant
Filed:
July 17, 2024
Date of Patent:
March 17, 2026
Assignee:
BAYA SYSTEMS, INC.
Inventors:
Joji Philip, Eric Norige, James Aldis, Honnahuggi Harinath Venkata Naga Ambica Prasad, Jatinkumar Vithalbhai Fultaria
Abstract: A method for a snoop filter includes using binary encodings and vector encodings to represent owner and sharers of cache lines of a cache. The vector encodings can be split across the multiple ways of the snoop filter via a vector range identifier and a common tag. Further, only vector ranges having at least one sharer from the sharers are allocated a way from the multiple ways.
Type:
Grant
Filed:
June 21, 2024
Date of Patent:
November 11, 2025
Assignee:
Baya Systems, Inc.
Inventors:
Swapnil Lotlikar, Joji Philip, James Aldis