Patents Assigned to Bayes Electronics Technology Co., Ltd
  • Patent number: 12493072
    Abstract: A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occurred during transient circuit simulation is determined. A transient debug mode is actuated responsive to determination of occurrence of the non-convergence error. The steps of performing the transient circuit simulation and determining whether a non-convergence error has occurred are repeated after actuation of the transient debug mode. Results of the transient circuit simulation are provided responsive to a determination of non-occurrence of a non-convergence error.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 9, 2025
    Assignee: Bayes Electronics Technology Co., Ltd
    Inventor: Gang Peter Fang
  • Patent number: 12387026
    Abstract: A method for automatic control of a simulation error in an analog circuit and a use thereof are provided. The method first determines a measurement object and acquires a simulation standard by simulating the measurement object. Then, the method performs simulation based on different parameters of a circuit netlist to acquire an electrical parameter and/or circuit performance evaluation indicator of the measurement object during a simulation process. The method forms a simulation sampling dataset based on a simulation option combination parameter and an error corresponding to the simulation standard. Finally, the method optimizes and analyzes the simulation sampling dataset based on an artificial intelligence algorithm to acquire a simulation option combination that meets a simulation error requirement and takes a least time. The solution achieves automatic selection of the simulation option combination, improving the accuracy of the simulation result.
    Type: Grant
    Filed: December 18, 2024
    Date of Patent: August 12, 2025
    Assignees: Bayes Electronics Technology Co., Ltd, Tessersoft Co., Ltd
    Inventors: Gang Fang, Wei Dong, Huanyu Liu, Zhenxin Zhao, Haojie Zhu, Ziqing Wang, Wei Wang
  • Publication number: 20250200262
    Abstract: A method for automatic control of a simulation error in an analog circuit and a use thereof are provided. The method first determines a measurement object and acquires a simulation standard by simulating the measurement object. Then, the method performs simulation based on different parameters of a circuit netlist to acquire an electrical parameter and/or circuit performance evaluation indicator of the measurement object during a simulation process. The method forms a simulation sampling dataset based on a simulation option combination parameter and an error corresponding to the simulation standard. Finally, the method optimizes and analyzes the simulation sampling dataset based on an artificial intelligence algorithm to acquire a simulation option combination that meets a simulation error requirement and takes a least time. The solution achieves automatic selection of the simulation option combination, improving the accuracy of the simulation result.
    Type: Application
    Filed: December 18, 2024
    Publication date: June 19, 2025
    Applicants: Bayes Electronics Technology Co., Ltd, Tessersoft Co., Ltd
    Inventors: Gang FANG, Wei DONG, Huanyu LIU, Zhenxin ZHAO, Haojie ZHU, Ziqing WANG, Wei WANG
  • Patent number: 12112111
    Abstract: In a method for analyzing a static analog integrated circuit layout, corresponding simulation netlists are generated from an integrated circuit layout by parasitic parameter extraction, and device-node hypergraph or graph structures reflecting a circuit topological structure are generated from the simulation netlists. Then, characteristics of RC local networks between ports of individual device groups to be matched are analyzed. An independent source current is provided at i-ports of the RC networks, AC analysis is performed on the RC local networks to acquire impedance values of j-ports at different frequencies, and then a circuit mismatch condition is determined by comparing the impedance values of the individual RC local networks.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: October 8, 2024
    Assignees: Bayes Electronics Technology Co., Ltd, Tessersoft Co., Ltd
    Inventors: Gang Fang, Wei Dong, Jiadong Gu, Zhenxin Zhao