Abstract: A method for a multi-antenna transmitter and receiver arrangement, the multi-antenna transmitter and receiver arrangement being comprisable in a wireless device, WD or in a transceiver node, TNode, the method comprising: obtaining a first plurality of arrays, each array comprising digital signals, each digital signal comprising information; performing first beamforming processing on the first plurality of arrays to obtain a second plurality of processed digital signals; performing second beamforming processing in a time domain on the second plurality of processed digital signals to obtain a third plurality of digital signals; combining the third plurality of digital signals to obtain a third plurality of combined digital signals; converting each of the third plurality of combined digital signals to respective analog signals; and transmitting each of the analog signals.

Abstract: A multi-antenna transceiver system is disclosed. The system comprises a group of transceiver chips, wherein each transceiver chip has a respective chip-associated (e.g., on-chip) frequency generator configured to provide a respective conversion frequency, and wherein each transceiver chip is configured to use the respective conversion frequency for on-chip frequency conversion of a transceiver signal. The system also comprises a controller adapted to cause configuration of the respective chip-associated frequency generator of at least one of the transceiver chips, wherein the configuration comprises dynamically setting the respective conversion frequency. In some embodiments, the controller comprises a single piece of circuitry separate from the transceiver chips. The single piece of circuitry is adapted to cause configuration of the respective chip-associated frequency generator of two or more of the transceiver chips.

Abstract: A digital pre-processing chip is disclosed. The digital pre-processing chip comprises an analog interface for transmitting and receiving analog signals to and from a plurality of analog Radio Frequency (RF) chips, and a digital interface for transmitting and receiving digital signals to and from a baseband chip. The digital pre-processing chip further comprises a plurality of Analog-to-Digital Converters (ADCs) for converting a plurality of analog signals received via the analog interface to a plurality of RX digital signals, and a plurality of Digital-to-Analog Converters (DACs) for converting a plurality of TX digital signals to a plurality of analog signals to be transmitted to the plurality of analog RF chips via the analog interface.

Abstract: A multi-antenna transceiver system including a group of transceiver chips, and a reference frequency generator configured to provide a reference frequency for each transceiver chip. Each transceiver chip has a respective chip-associated (e.g., on-chip) frequency generator configured to provide a respective conversion frequency based on the reference frequency, wherein each respective conversion frequency is higher than the reference frequency. Each transceiver chip is configured to use the respective conversion frequency for on-chip frequency conversion of a transceiver signal. The reference frequency may be provided directly to each transceiver chip of the group or may be provided directly to a first transceiver chip of the group and to a second transceiver chip of the group via the first transceiver chip.

Abstract: This disclosure relates to a transceiver element comprising receiving circuitry, down-converting circuitry, extracting circuitry and output circuitry. The receiving circuitry is configured to receive a radio frequency signal via an antenna element associated with the receiving circuitry. The radio frequency signal comprises a first received signal part and a second received signal part. The down-converting circuitry is configured to down-convert the radio frequency signal to provide a down-converted signal. The down-converted signal comprises a first down-converted signal part corresponding to the first received signal part and a second down-converted signal part corresponding to the second received signal part. The extracting circuitry is configured to extract at least the second down-converted signal part from the down-converted signal. The output circuitry is configured to provide an output signal comprising a first output signal part and a second output signal part.

Abstract: A MIMO transceiver has a plurality of analog processing subsystems that each includes at least one antenna, a duplexer, at least one power amplifier, at least one mixer, an interface connectable to a baseband processing subsystem, and the MIMO transceiver has one or more analog radio frequency processing chips. Each analog processing subsystem of the plurality of analog processing subsystems is on a single one of the analog radio frequency processing chips, and each analog radio frequency processing chip comprises a metallization on at least one side of the chip and wherein the metallization comprises integration of the at least one antenna.

Abstract: An analog processing subsystem is disclosed. Said subsystem comprising at least one antenna (202,302), a duplexer (202a,302a), at least one power amplifier (203a,203b), at least one mixer (204a,204b, 304a, 304b) and an interface connectable to a baseband processing subsystem. The at least one mixer (204a,204b,304a,304b) is adapted to down-convert and inphase/quadrature—IQ—demodulate a received analog radio frequency signal, received by the at least one antenna (202,302), to provide a received analog baseband signal and to IQ-modulate and up-convert a transmit analog baseband signal, to be transmitted by the at least one antenna (202, 302), to provide a transmit analog radio frequency signal. The analog processing subsystem is comprised on a single analog radio frequency processing chip (201,301) comprising a metallization on at least one side of the chip for integration of the at least one antenna (202,302).