Abstract: A multi-iteration method for compressing a deep neural network into a sparse neural network without degrading the accuracy is disclosed herein. In an example, the method includes determining a respective initial compression ratio for each of a plurality of matrices characterizing the weights between the neurons of the neural network, compressing each of the plurality of matrices based on the respective initial compression ratio, so as to obtain a compressed neural network, and fine-tuning the compressed neural network.

Abstract: Hardware accelerator for compressed Long Short Term Memory (LSTM) is disclosed. The accelerator comprise a sparse matrix-vector multiplication module for performing multiplication operation between all sparse matrices in the LSTM and vectors to sequentially obtain a plurality of sparse matrix-vector multiplication results. A addition tree module are also included for accumulating a plurality of said sparse matrix multiplication results to obtain an accumulated result. And a non-linear operation module passes the accumulated results through an activation function to generate non-linear operation result. That is, the present accelerator adopts pipeline design to overlap the time of data transfer and computation for compressed LSTM.

Abstract: Systems, apparatus and methods are provided for accelerating a complex neural network by fixed-point data quantization. An Artificial Neural Network (ANN) has branches and comprises convolutional layers CONV 1, CONV 2, . . . CONV n, fully connected layers FC 1, FC 2, . . . , FC m, and concatenation layers CONCAT1, CONCAT2, . . . , CONCAT L. n, m and L are positive integers. The ANN may be optimized by a method comprising: converting output of each of the CONV, FC and CONCAT layers into fixed-point numbers, identifying at least one sub-network from the ANN and for each sub-network, modifying the fixed-point range of each output of the previous-level layers of the CONCAT layer on the basis of the fixed-point range of the CONCAT layer. The sub-network has a CONCAT layer as its output. The CONCAT layer receives at least two outputs of previous-level layers as inputs and concatenates the inputs into one output.

Abstract: The present invention relates to artificial neural network, for example, convolutional neural network. In particular, the present invention relates to how to implement and optimize a convolutional neural network based on an embedded FPGA. Specifically, it proposes an overall design process of compressing, fix-point quantization and compiling the neural network model.

Abstract: The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, a first instruction unit, a second instruction unit, an instruction distributing unit, a data transferring controller, a buffer module and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.