Abstract: A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

Abstract: A transistor and a fabrication method thereof are provided. The transistor includes a substrate, a low-dimensional material layer, a gate, a source, a drain, a gate dielectric layer, and spacers. The low-dimensional material layer is provided above the substrate. The source is located at a first side of the gate. The drain is located at a second side of the gate. The gate dielectric layer is provided between the gate and the low-dimensional material layer. The spacers are provided between the source and the gate and between the drain and the gate, respectively. The substrate has fixed charges, or interface dipoles are formed by the substrate and an insulating dielectric layer. The insulating dielectric layer includes at least one of the gate dielectric layer and the spacers. In the transistor, the low-dimensional material layer may be electrostatically doped in various ways, which have low cost and are better compatible with the fabricating process of the transistor.

Abstract: A transistor and a fabrication method thereof are provided. The transistor includes a substrate, a low-dimensional material layer provided above the substrate, a gate, a source, a drain, a gate dielectric layer, and spacers. The source is located at a first side of the gate. The drain is located at a second side of the gate. The gate dielectric layer is provided between the gate and the low-dimensional material layer. The spacers are provided between the source and the gate and between the drain and the gate, respectively, in which dipoles are formed in the spacers to electrostatically dope the low-dimensional material layer. In the transistor, the dipoles in the spacers may be used to electrostatically dope the channel in the spacer region.

Abstract: A transistor and a fabrication method thereof are provided. The transistor includes a substrate, a low-dimensional material layer, a gate, a source, a drain, a gate dielectric layer, and spacers. The low-dimensional material layer is provided above the substrate. The source is located at a first side of the gate. The drain is located at a second side of the gate. The gate dielectric layer is provided between the gate and the low-dimensional material layer. The spacers are provided between the source and the gate and between the drain and the gate, respectively, and have fixed charges. In the transistor, the fixed charges in the spacers are used to electrostatically dope the channel material in the spacer region.

Abstract: A field effect transistor (FET), a method of fabricating a field effect transistor, and an electronic device, the field effect transistor comprises: a source and a drain, the source being made of a first graphene film; a channel disposed between the source and the drain, and comprising a laminate of a second graphene film and a material layer having semiconductor properties, the second graphene film being formed of bilayer graphene; and a gate disposed on the laminate and electrically insulated from the laminate.

Abstract: The present disclosure discloses a method for forming a high-density aligned carbon nanotube film. The method includes injecting a carbon nanotube solution into a container, and adding a dispersant to form a carbon nanotube-dispersant composite. The method also includes adding a substance that interacts with the carbon nanotube-dispersant composite and then dispersing the obtained carbon nanotube solution using water ultrasonic or probe ultrasonic to obtain a carbon nanotube solution containing a dispersant. Then a large-area or patterned high-quality aligned carbon nanotube film can be formed on a substrate by using processes such as pulling, injection dripping or printing. The method is low-cost and suitable for the preparation of large-area high-density aligned carbon nanotubes, and satisfies various needs for industrial application of carbon-based integrated circuits.

Abstract: The present disclosure discloses a device and a method for preparing a high-density aligned carbon nanotube film. The device includes a container main body, a buffer partition plate and a solvent lead-out part. The buffer partition plate is located at a lower part of the container main body. The solvent lead-out part communicates with an interior of the container main body through a through hole in a side wall of the container main body and extends to an outside of the container main body. The method includes injecting a carbon nanotube solution into a container; immersing a substrate in the carbon nanotube solution; injecting a sealing liquid that is immiscible with the carbon nanotube solution along the substrate or the side wall of the container main body; and leading the solvent out or pulling the substrate such that the liquid surface of the substrate undergoes relative motion.

Abstract: A field effect transistor (FET), a method of fabricating the field effect transistor, and an electronic device are provided. The field effect transistor comprises: a source and a drain, the source being made of a Dirac material (103); a channel disposed between the source and the drain, and doped opposite to the source; and a gate (106) disposed on the channel and electrically insulated from the channel.

Abstract: A field effect transistor, a method of manufacturing the field effect transistor, and an electronic device are provided, wherein the field effect transistor comprises: a source(105) formed of a Dirac material(103) and a drain(107); a channel(102) disposed between the source(105) and the drain(107); and a source control electrode(108) disposed on the source(105) and for controlling the doping of the Dirac material(103) such that the Dirac material(103) and the channel(102) are doped in an opposite manner; and a gate(106) disposed on the channel(102) and electrically insulated from the channel(102).

Abstract: A field effect transistor (FET), a method of fabricating the field effect transistor, and an electronic device are provided. The field effect transistor comprises: a source and a drain, the source being made of a Dirac material (103); a channel disposed between the source and the drain, and doped opposite to the source; and a gate (106) disposed on the channel and electrically insulated from the channel.

Abstract: A field effect transistor (FET), a method of fabricating a field effect transistor, and an electronic device, the field effect transistor comprises: a source and a drain, the source being made of a first graphene film; a channel disposed between the source and the drain, and comprising a laminate of a second graphene film and a material layer having semiconductor properties, the second graphene film being formed of bilayer graphene; and a gate disposed on the laminate and electrically insulated from the laminate.

Abstract: A field effect transistor, a method of manufacturing the field effect transistor, and an electronic device are provided, wherein the field effect transistor comprises: a source (105) formed of a Dirac material (103) and a drain (107); a channel (102) disposed between the source (105) and the drain (107); and a source control electrode (108) disposed on the source (105) and for controlling the doping of the Dirac material (103) such that the Dirac material (103) and the channel (102) are doped in an opposite manner, and a gate (106) disposed on the channel (102) and electrically insulated from the channel (102).