Abstract: Aspects of the present disclosure describe a cache system that is co-managed by software and hardware that obviates use of a cache coherence protocol. In some embodiments, a cache would have the following two hardware interfaces that are driven by software: (1) invalidate or flush its content to the lower level memory hierarchy; (2) specify memory regions that can be cached. Software would be responsible for specifying what regions can be cacheable, and may flexibly change memory from cacheable and not, depending on the stage of the software program. In some embodiments, invalidation can be done in one cycle. Multiple valid bits can be kept for each tag in the memory. A vector “valid bit vec” comprising a plurality of bits can be used. Only one of two bits may be used as the valid bit to indicate that this region of memory is holding valid information for use by the software.

Abstract: Aspects of the present disclosure are presented for a multi-threaded system configured to efficiently handle dynamic thread spawning. When a child thread is spawned when executing a program, it may be possible that the parent thread needs the child thread ID for initialization. However, to get the child thread ID, the child thread may need to be generated, and once it is generated, it could be executed immediately, even before the initialization finishes, causing an error. The present disclosure introduces a memory efficient solution through use of a control circuit configured to control when child threads can be executed while still enabling the parent threads to obtain the child thread IDs.

Abstract: Aspects of the present disclosure describe a cache system that is co-managed by software and hardware that obviates use of a cache coherence protocol. In some embodiments, a cache would have the following two hardware interfaces that are driven by software: (1) invalidate or flush its content to the lower level memory hierarchy; (2) specify memory regions that can be cached. Software would be responsible for specifying what regions can be cacheable, and may flexibly change memory from cacheable and not, depending on the stage of the software program. In some embodiments, invalidation can be done in one cycle. Multiple valid bits can be kept for each tag in the memory. A vector “valid bit vec” comprising a plurality of bits can be used. Only one of two bits may be used as the valid bit to indicate that this region of memory is holding valid information for use by the software.

Abstract: Aspects of the present disclosure are presented for a multi-threaded system configured to efficiently handle dynamic thread spawning. When a child thread is spawned when executing a program, it may be possible that the parent thread needs the child thread ID for initialization. However, to get the child thread ID, the child thread may need to be generated, and once it is generated, it could be executed immediately, even before the initialization finishes, causing an error. The present disclosure introduces a memory efficient solution through use of a control circuit configured to control when child threads can be executed while still enabling the parent threads to obtain the child thread IDs.