Abstract: Disclosed are a semiconductor device, a manufacturing method therefor, and an electronic equipment, the semiconductor device includes: at least one vertical channel transistor disposed on a base substrate, and a bit line; the transistor includes a semiconductor pillar extending along a direction perpendicular to the base substrate, the semiconductor pillar includes a channel region, and a first region and a second region respectively disposed on two sides of the channel region, the second region is disposed between the base substrate and the first region, the bit line is in contact with the second region, and a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms/square centimeter.

Abstract: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. The C-shaped ferroelectric layer serves as a memory layer of the memory device.

Abstract: A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Abstract: A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Abstract: Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

Abstract: Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.

Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

Abstract: A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.

Abstract: The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Abstract: The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Abstract: Provided is a semiconductor structure. The semiconductor structure includes a substrate including a die region and a non-die region, wherein an accommodation recess is formed in a side of the substrate and positioned in the non-die region; a buffer disposed in the accommodation recess; a functional film layer disposed on the side, where the accommodation recess is formed, of the substrate; and a passivation layer covering the functional film layer and the substrate. A buffer cavity with an opening facing away from the substrate is formed in the buffer. An orthographic projection of the functional film layer on the substrate is within the die region. A first through-via is formed in the passivation layer. An orthographic projection of the first through-via on the substrate is at least partially overlapped with an orthographic projection of the opening on the substrate. The opening is in communication with the first through-via.