Abstract: The disclosure provides a method for distributing instructions in a reconfigurable processor. The reconfigurable processor includes an instruction fetch module, an instruction sync control module and an instruction queue module. The method includes: configuring a format of a Memory Sync ID Table of each instruction type, obtaining a first memory identification field and a second memory identification field of each instruction, obtaining one-hot encodings of first and second memory identification fields, obtaining a sync table and executing each instruction of a plurality of to-be-run instructions.

Abstract: A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.

Abstract: An instruction scheduling method and an instruction scheduling system for a reconfigurable array processor. The method includes: determining whether a fan-out of a vertex in a data flow graph (DFG) is less than an actual interconnection number of a processing unit in a reconfigurable array; establishing a corresponding relationship between the vertex and a correlation operator of the processing unit; introducing a register to a directed edge, acquiring a retiming value of each vertex; arranging instructions in such a manner that retiming values of the instruction vertexes are in ascending order, and acquiring transmission time and scheduling order of the instructions; folding the DFG, placing an instruction to an instruction vertex; inserting a register and acquiring a current DFG; and acquiring a common maximum subset of the current DFG and the reconfigurable array by a maximum clique algorithm, and distributing the instructions.

Abstract: The present disclosure provides a processor array and a multiple-core processor. The processor array includes a plurality of processing elements arranged in a two-dimensional array, a plurality of first load units correspondingly arranged and connected to the processing elements of the first edge row, respectively, a plurality of second load units correspondingly arranged and connected to the processing elements of the first edge column, respectively, a plurality of first store units correspondingly arranged and connected to the processing elements of the second edge column, respectively, a plurality of second store units correspondingly arranged and connected to the processing elements of the second edge row, respectively.

Abstract: A data storage method includes: obtaining memory banks of arithmetic data; generating undetermined memory bank numbers of the memory banks sequentially; scanning storage dimensions of the arithmetic data to obtain the undetermined memory bank numbers, filling elements to make the undetermined memory bank numbers continuous if the undetermined memory bank numbers of two adjacent dimensions are not continuous; taking as a current transformation vector through a greedy algorithm a determined transformation vector where conflict is least and the number of the filling elements is smallest; generating current memory bank numbers of the memory banks according to the current transformation vector; converting each of the current memory bank numbers into a physical storage bank address through an offset function to obtain a corresponding internal offset address; and storing the arithmetic data into the memory banks according to the current memory bank numbers and the internal offset addresses.