Patents Assigned to Bell Semiconductor, LLC
  • Patent number: 12278234
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FIN FET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: April 15, 2025
    Assignee: Bell Semiconductor, LLC
    Inventors: Qing Liu, Prasanna Khare, Nicolas Loubet
  • Patent number: 12191309
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Grant
    Filed: February 28, 2024
    Date of Patent: January 7, 2025
    Assignee: Bell Semiconductor, LLC
    Inventors: Pierre Morin, Nicolas Loubet
  • Publication number: 20240203995
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Applicant: Bell Semiconductor, LLC
    Inventors: Pierre MORIN, Nicolas LOUBET
  • Patent number: 11948943
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 2, 2024
    Assignee: Bell Semiconductor, LLC
    Inventors: Pierre Morin, Nicolas Loubet
  • Publication number: 20230260846
    Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Applicant: Bell Semiconductor, LLC
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Publication number: 20230197720
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FIN FET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 22, 2023
    Applicant: Bell Semiconductor, LLC
    Inventors: Qing LIU, Prasanna KHARE, Nicolas LOUBET
  • Patent number: 11670554
    Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 6, 2023
    Assignee: Bell Semiconductor, LLC
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Publication number: 20230121119
    Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Applicant: Bell Semiconductor, LLC
    Inventors: Nicolas LOUBET, Prasanna KHARE
  • Patent number: 11610886
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: March 21, 2023
    Assignee: Bell Semiconductor, LLC
    Inventors: Qing Liu, Prasanna Khare, Nicolas Loubet
  • Patent number: 11587928
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: February 21, 2023
    Assignee: Bell Semiconductor, LLC
    Inventors: Pierre Morin, Nicolas Loubet