Abstract: The disclosed clock adjustment method and apparatus utilizes a periodically transmitted positive or negative predetermined fixed increment clock phase adjustment signal to phase adjust the clocks of the system. The transmitter clock is periodically compared with a common reference clock and a fixed increment clock adjustment signal is transmitted to the receiver which adjusts its clock by applying the fixed increment clock adjustment signal to the common reference clock. The utilization of a predetermined fixed increment clock phase adjustment signal eliminates the need to send the resolution of the clock adjustment and hence reduces the number of data bits required to send clock information over the communication channel.

Abstract: An integrated data processing and communication service is provided by a system which comprises a plurality of nodes interconnected via a packet-switched transport network. Each node includes a database processor and at least one node processor, with a number of terminals and hosts being connected to the latter via at least one front-end processor. Processes existing with each node processor are two types--application layer processes which perform "useful work" on behalf of the customers and the vendor of the service, and control layer processes, each of which manages, or provides some part of, the service itself. The processors are virtual memory processors and the program region of the virtual address space of each process includes both a process-specific image and shared image.

Abstract: A multi-stage time division switch interconnects a plurality of processors that individually communicate over one or more channels at various signalling rates. Any processor may initiate a call and request that a connection be set by the switch. The switch assigns one or more time slots to the call and gathers or distributes data over the interconnecting channels through the utilization of polling techniques, thereby creating a virtual circuit through the combination of a time division switch and a polled communication line.

Abstract: Amplifiers, optionally having complementary (positive and negative) outputs, are connected to a matrix of input and output conductors (where the output conductors are each a pair for the case of complementary amplifier outputs). Each connection is implemented with a resistors R.sub.ij =R.sub.ji connecting the output(s) of amplifiers j to the input of amplifiers i, and vice versa, where i and j are the ith and jth amplifiers not necessarily in sequence. The value of each resistor is selected for the nature of the decisional operation intended to satisfy the following circuit equation of motion ##EQU1## where V.sub.j =g(u.sub.j) the output of amplifier j due to an input u.sub.i, C.sub.i is the input capacitance of amplifier i, and R.sub.i is the equivalent of p.sub.i and R.sub.ij according to the equation ##EQU2## and R.sub.ij =R.sub.ji.

Abstract: A multi-stage time division switch interconnects processors communicating over one or more channels on time division lines. One of the processors is designated as a common processor to provide the switching "mapping" information for the various stages of the switch sending the switching information to the memory and logic of each switched stage over dedicated channels which include channels on the time division line emanating from the common processor and time division channels which pass through several switches until the memory of the applicable switch is accessed.

Abstract: The occurrence of a transmission error which produces a multibit error burst in the decrypted version of a composite speech and synchronization encrypted signal using a one-bit cipher feedback or similar encryption scheme is detected by monitoring the decrypted signal to detect synchronization errors. Upon detection of an error, the decrypted speech output is muted or disabled to avoid the annoying audible click otherwise produced.

Abstract: A digital processor based voiceband modem that provides computers and terminals access to telephone lines and performs line control functions to originate, answer and terminate data calls in addition to converting baseband signals to voiceband and voiceband signals to baseband. The modem utilizes a signal processor that executes various signal converting algorithms under control of selected sets of instructions and further utilizes a digital processor that executes line control algorithms for alternative modes (i.e., originate or answer) of the data modem. An outgoing or incoming call enables the appropriate mode and, during the execution of the corresponding line control algorithm, various sets of instructions are selected to execute signal converting algorithms appropriate for the enabled mode of a specific one of various data modem types.

Abstract: A digital computer is arranged to process data through an arithmetic logic unit in response to instructions residing sequentially in an instruction register, each instruction requiring a single instruction interval for fetching data from a selected source in a store, processing the data in the arithmetic logic unit, and storing the result of processing the data into a selected destination in the store. Means are provided for moving a single bit from any selected one of a plurality of bit positions in the selected source to any selected bit position of a plurality of bit positions in the selected destination during a single instruction interval without affecting the state of any other bit of the selected destination.

Abstract: A detector circuit detects one of two impedances presented by a communication line for each one of a plurality of operative modes. The circuit comprises a network having three parallel branches. The first includes two serially connected resistors which develop a reference potential in response to current flowing in the line. The second branch includes two oppositely poled light-emitting diodes (LEDs) which form a sensor to detect current flow in the line in either direction. The third branch includes a varistor to limit the magnitude of unexpected potentials applied to the sensor. When the magnitude of the reference potential is sufficient to forward bias either LED and the magnitude of the current is greater than a predetermined level, one of the LEDs will generate an output signal representative of one impedance of the line. Otherwise, the LEDs generate a second output representative of the other impedance of the line in a particular operative mode.

Abstract: The battery feed circuit (FIG. 3) provides a balanced dc feed current (I.sub.TR) to a 2-wire telecommunications path. The dc current in each conductor is generated by a bidirectional current source (103 or 104) which is responsive to one of a complementary pair of first control signals (S.sub.1, S.sub.1) along with a second control signal (S.sub.2). The complementary pair of first control signals is generated by a feedback circuit (105) which monitors the differential mode voltage (V.sub.TR) across the path. To reduce power consumption, the complementary pair of first control signals is a nonlinear function of the differential mode voltage. The resulting battery feed profile (FIG. 2) reduces the current on short path lengths. Longitudinal balance is provided by the second control signal which varies the currents generated by each bidirectional current source by equal amounts. This second control signal is generated by a second feedback circuit (109) which monitors the common mode voltage across the path.

Abstract: Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of requesting ports. During bus contention time, each requesting unit synchronously and sequentially applies the digits of its unique priority code to the bus beginning with the most significant digit. Each requesting unit remains in contention only so long as each digit it applies is greater than or equal to the digit applied by any other unit. After the application of all digits, only the requesting unit having the highest code remains in contention and it seizes the bus. A polarity control conductor is provided, selectively altering the preference that is normally specified by the assigned priority codes. The application of a reversal signal to this conductor for a given interval of time causes each requesting unit to invert each bit of its priority code it applies to the bus during this time interval.

Abstract: An improved computer program method for rapidly copying data that operates in a time-shared operating system environment. Two concurrent computer program processes are employed, each copying data from the input device to the output device through its own memory buffer. The two processes communicate with one another through interprocess communication means provided by the operating system in order to coordinate their activity. As a result, double buffered overlapped input/output is achieved using only synchronous input/output commands provided by the operating system.

Abstract: A video signal actuated switch is disclosed having general application in the area of video home entertainment systems. The present video signal actuated switch comprises an impedance matching circuit (200) for matching the impedance of an incoming video signal (VS) for display. A high impedance amplifier (201), having an associated filtering circuit (201a), amplifies a particular band of frequencies comprising a known component frequency of the video signal (VS). No significant degradation of the standard video signal results from the application of the impedance matching circuit (200) in combination with the amplifier circuit (201). An actuator circuit (202) provides a signal (F) responsive to the output of the amplifier circuit (201) to a control circuit (203). The control circuit (203), responsive to signal (F), provides a control signal (E) for controlling the selection of video inputs to a video terminal (100) and for controlling or powering an RF modulator circuit (206).

Abstract: The present invention relates to hybrid mode feeds which are capable of handling very wide bandwidths. In the present feed arrangements, a dominant TE.sub.11 mode is converted to the HE.sub.11 hybrid mode which is then launched. The TE.sub.11 to HE.sub.11 mode conversion is achieved by inserting a circular dielectric rod (12) into a flared end (11) of a smooth-walled cylindrical feedhorn until a small cylindrical section of the dielectric rod engages with the inner wall (15) of the unflared portion of the feedhorn. In one feed arrangement, the other end of the dielectric rod is similarly inserted into a flared end (21) of a corrugated cylindrical feedhorn section (22) until a short longitudinal section of the cylindrical portion of the rod is concentric with the corrugations of an unflared section of the feedhorn to provide a transition for the HE.sub.11 mode into the corrugated waveguide for subsequent launch.

Abstract: A semiconductor structure contains two interconnected gated diode switches in a common dielectrically isolated semiconductor tub. This structure functions as a bidirectional switch. A gate region physically located between the two switches provides electrical isolation to allow proper operation.

Abstract: An adaptive distributed message routing algorithm that may be implemented in a computer program to control the routing of data messages in a packet message switching digital computer network. Network topology information is exchanged only between neighbor nodes in the form of minimum spanning trees, referred to as exclusionary trees. An exclusionary tree is formed by excluding the neighbor node and its links from the tree. From the set of exclusionary trees received a route table and transmitted exclusionary trees are constructed.

Abstract: An echo canceller for passband data signals is comprised of a pair of real passband filters which generate samples of the echo replica in response to respective streams of rotated data symbol components.

Abstract: In a heterostructure distributed Bragg reflector laser, at least one multilayer waveguide substantially comprised of a silicon dielectric compound is monolithically integrated with an active semiconductor heterostructure medium. Bragg reflectors are properly disposed within the waveguide.

Abstract: Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. A plurality of status flip-flops is provided in each port for generating port parameter bits. The generated parameter bits are applied to the bus as the most significant bits of a dynamic port priority code during contention time. However, the selective application of a mask signal to a mask conductor during contention time causes each requesting port to ignore any parameter bits on the bus as long as the mask signal remains. This returns control of the port preference to any unmasked parameter bits and to the assigned port priority codes.

Abstract: Multibit digital signals, being telephone call signal samples from different simultaneous call connections and coded in an ordered coding system, are stored in different locations of a first buffer store. The respective signals are coupled through a stored program controlled switching processor to randomly selectable locations of a second buffer store for transmission to corresponding respective different call destinations. A register is provided in the switching processor for temporarily storing each signal as it is coupled through the processor. Also included in the processor is the capability for additional selectable processing of those coupled signals en route.