Abstract: A power-down network is included in a tristate TTL circuit to reduce power dissipation in the high impedance third state while permitting high switching speeds during bistate operation of the circuit. The power-down circuit includes a power-down transistor connected in series between the collector resistor and collector of the phase splitter transistor. The base of the phase splitter transistor is connected through a diode to the disabling gate. A first resistor having a significantly higher value than the collector resistor is connected between the base of the power-down transistor and the V.sub.CC terminal. When the circuit is in the high impedance state, the power-down transistor is turned off to interrupt current flow through the collector resistor, and a relatively high impedance current path through the first resistor to the disabling gate is substitute for an otherwise relatively low impedance current path through the collector resistor.

Abstract: DPCM or PCM samples which have been quantized at a transmitter are assigned a representative value associated with one of a plurality of mutually exclusive quantization levels, each having predefined upper and lower limits. The sample values are reconstructed at the receiver using (in addition to the representative value) information regarding the quantizer characteristics as well as information derived from spatially or temporally correlated samples. In DPCM systems, the same technique can also be used at the transmitter to improve prediction of the present sample by improving reconstruction of previously processed samples.

Abstract: An electrical device having a nonlinear current-voltage characteristic is described which uses TiO.sub.2, a Group IIA element such as barium, calcium and strontium in an amount greater than 0.0 and generally less than approximately 1.0 mole percent, a Group VB element such as niobium in an amount generally less than 5.0 mole percent.

Abstract: In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the transistors in the string, the switching-delay is not significantly reduced by uniformly increasing the conduction channel widths of the transistors in the string. However, according to the present invention, a substantial reduction in the switching delay of such a circuit may be obtained by scaling the conduction channel widths of the transistors in the string so as to provide a positive gradient in conduction channel widths along the string in the direction from the output terminal to the power supply terminal. It is particularly advantageous to use exponential scaling of the conduction channel widths.

Abstract: In planar silicon semiconductor devices of the PN junction type, field plates overlie the silicon dioxide-silicon nitride film on the device surface to inhibit inversion formation of conductive channels on the device surface. The field plates are connected to a more heavily doped zone on one side of a PN junction and extend some distance over the lightly doped zone on the other side of the PN junction.At high reverse biases, the presence of trapping centers produces a charge level at the device surface, resulting in current channeling which produces excessive reverse leakage current. This effect is avoided or reduced by omitting the silicon nitride layer in a portion overlying the more lightly doped zone and spaced away from the PN junction boundary. This omission eliminates a portion of the oxide-nitride interface which appears to be the locus of such trapping centers.

Abstract: An electret transducer for producting a highly directional response characteristic comprises a backplate (18) and, superimposed thereon, an electrostatically charged electret foil (10). The electrostatic charge varies according to a predetermined relationship. The sensitivity of the electret transducer, at any point thereon, is directly proportional to the electrostatic charge on the electret foil at that point.

Abstract: A voltage detector circuit for detecting a DC voltage on a line in the presence of a substantially fixed frequency AC voltage. The circuit may be used to detect call originations on a telephone line having longitudinal AC voltages induced thereon. The circuit compares the instantaneous voltage on the line with a reference level and repetitively increments a counter when the instantaneous voltage exceeds the reference level and repetitively decrements the counter when the instantaneous voltage does not exceed the reference level. After operating the counter for a time interval substantially equal to the period of the fixed frequency AC voltage, the most significant bit of the counter will indicate whether the DC voltage on the line is above the reference level. The circuit may also be used to detect call terminations on the line.

Abstract: An acoustic transducer for producing highly directional characteristics comprises a metalized backplate (130) facing the flat surface (134) of an electrostatically charged electret foil (132). The thickness of the electret foil varies along the length thereof according to a predetermined relationship. The sensitivity of the electret transducer varies directly with the thickness of the electret foil.

Abstract: An electret transducer comprises an electrostatically charged electret foil (10) superimposed directly over a selectively metalized rough surface (16) of a backplate (18). Selective metalization is realized by depositing a thin metal layer (20), the contour of which is defined by a predetermined relationship, over the rough surface (16). The sensitivity of the electret transducer at any point thereon is directly proportional to the width of the metal layer on the backplate. The response characteristic of the electret transducer comprises a main lobe and a plurality of sidelobes below a preselected threshold.

Abstract: A process for fabricating a high speed bipolar transistor is described wherein the collector, base and emitter layers are first grown using molecular beam epitaxy (MBE). A mesa etch is performed to isolate a base-emitter region, and a contact layer is grown using MBE over this isolated region to make contact with the thin base layer. The contact layer is selectively etched to expose the emitter layer, and metal is deposited to fabricate emitter, base and collector contacts.

Abstract: A rough surfaced backplate has deposited thereon a metallic electrode having a plurality of large areas interconnected by thin strips. The large areas are symmetrically located on opposite sides of the center of the metallic electrode. Furthermore, the distances between the areas is nonlinear. Superimposed on the metallic electrode is an electret foil having a uniform electrostatic charge deposited on the polymer surface thereof.

Abstract: An ac plasma panel is arranged with selective row and column shifting capability. Shifting in both the horizontal and vertical directions is accomplished by arranging for display site discharge transportation under control of eight control conductors with four conductors serving the horizontal direction and four conductors serving the vertical direction. The eight control conductors are used to provide sustain pulses for the ON display sites, and, using the same conductors, an out-of-phase pulse is used to freeze any of the display sites in any row or column while allowing display site transfer to occur selectively in any other row or column.

Abstract: Selected portions of the interior surface of a substrate tube, or of the cladding or core layers deposited on the interior surface of the substrate tube, are treated by one or more process steps such as shaping, diffusing, leaching, or depositing. Patterning processes such as photolithography and lift-off are employed to define the selected portions. The resulting core and/or cladding layers of the fiber can be made to have a variety of geometric shapes and composition profiles useful, for example, in realizing birefringent fibers and multiple-core fibers. Also described is the similar treating of metal layers and the incorporation of such layers into the fiber.

Abstract: A fault and error detection arrangement for detecting transmission and routing errors made by systems in which a central data transmitter/receiver (601, 610) bidirectionally intercommunicates with peripheral circuits (620) through an interconnection arrangement (604). The parity bits of certain data words transmitted by the central data transmitter (601) are intentionally inverted by a central parity inverter (602), in a known sequence. Data words transmitted by the central data transmitter (601) are routed by the interconnection arrangement (604) to the peripheral circuits (620) where parity is checked by a peripheral parity checker (621) and a parity invert signal is generated when an inverted parity data word is found. A peripheral parity inverter (623) included in each peripheral circuit (620) responds to the parity invert signals by inverting the parity bit of the next data word transmitted by a peripheral data transmitter (622) also included in each peripheral circuit (620).

Abstract: A high performance operational amplifier 12 circuit 10 nulls the offset voltage by means of switched capacitors (C.sub.2, C.sub.3) and holds the signal output 18 during the nulling. Switching is in response to two non-overlapping pulse trains .phi..sub.1, .phi..sub.2. During an output valid phase .phi..sub.1, with the signal input source connected to the inverting input 14 of the amplifier 12, an offset voltage storage capacitor C.sub.2 is connected between the non-inverting input 16 and ground. A signal storage capacitor C.sub.3 is connected between the output 18 and ground. During a nulling phase .phi..sub.2, the signal storage capacitor C.sub.3 is disconnected from ground and connected between the output 18 and the inverting input 14. The previously grounded side of the offset voltage storage capacitor C.sub.2 is switched to the inverting input port 14. The non-inverting input port 16 is grounded. The offset storage capacitor C.sub.

Abstract: The present invention is a programmed logic array (PLA) which implements IF, THEN, ELSE, or CASE statements. This is accomplished through the use of combinatorial logic located between the DECODER and ROM arrays of the PLA.

Abstract: A directional electret transducer comprises an electret foil and a metalized backplate the effective air gap thickness therebetween varying according to a predetermined relationship. The sensitivity of the electret transducer is directly proportional to the effective air gap thickness. The effective air gap thickness is realized in three ways: first, a plurality of equal diameter holes are drilled to varying depths in the aforesaid backplate; second, a plurality of holes of varying diameters are drilled through the aforesaid backplate; third, a plurality of equal diameter holes are drilled through the aforesaid backplate, the density of the holes varying. In each of the aforesaid three ways, the variation is according to the predetermined relationship.

Abstract: A system (FIG. 1) for interrogating the ON-OFF status of an electrical switch (31) comprises a semiconductor body (4) containing a PN junction and means (5) for electrically connecting an auxiliary switch (32) coupled to the interrogated switch, or alternately (FIG. 2) the interrogated switch (32), across the PN junction. Light (7) of a first wavelength incident on the semiconductor body causes light of a second wavelength (11) to be emitted from the body when the switch is open (OFF), whereas no light is emitted from the body when the switch is closed (ON). Therefore, photoelectric detection of the emission vs. non-emission of light of the second wavelength from the semiconductor body indicates the OFF vs. ON status of the switch.

Abstract: Apparatus (16) for cleaning or lubricating inaccessible pin arrays of an electrical interconnection backplane (10). A connector block (18) with contacts removed is mounted on the end of a dummy circuit board (17). The connector block (18) is slotted across the contact chambers (20), the slot (21) having an absorbent element (24) fitted therein. The element (24), which may be of a polyurethane foam, is saturated with a cleaning or lubricating agent. To clean or lubricate the pins (11), the dummy board (17) is fitted between the guide frames until the backplane pins (11) pierce the absorbent element (24), the latter being "selfhealing" when the appartus is withdrawn.

Abstract: Cu-Ni-Sb alloys have been discovered having a two-phase or multiphase state at low levels of antimony, and alloys in such state have high strength, high ductility, and high electrical conductivity. Tensile strengths in the range of 80,000-160,000 psi have been achieved, and electrical conductivity in the range of 30-65 percent of the conductivity of copper.Alloys of the invention can be made by processing involving homogenizing, rapid cooling, cold working, and aging; for maximized electrical conductivity, dual combined steps of cold working and aging are beneficial.