Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

Abstract: Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

Abstract: Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor.

Abstract: Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

Abstract: Novel three-dimensional DRAM structures are disclosed, together with methods of making the same. Each DRAM cell comprises a vertical transistor and a storage capacitor stacked vertically. Storage capacitors are arranged in a rectangular pattern in the array of DRAM cells. This arrangement improves the area efficiency of storage capacitors over honeycomb type. A first embodiment of the present disclosure uses cup-shaped storage capacitors. The exterior of the cup as well as the interior may contribute to the capacitance. In a second embodiment, a single capacitor pillar forms the internal electrode of each storage capacitor. A third embodiment employs double-pillar storage capacitors. Common to all embodiments are options to dispose contact plugs between vertical transistors and storage capacitors, dispose an etch-stop layer over the gate of vertical transistors, dispose one or more mesh layers for storage capacitors, and widen semiconductor pillars within available space in bit-line direction.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

Abstract: A method for fabricating semiconductor memory device, includes providing a semiconductor substrate; forming a lower region which includes a first data storage device, which is carried by the semiconductor substrate; forming a switching device which is carried by the first data storage device; and forming an upper region which includes a second data storage device, which is carried by the switching device. The step of forming the first storage device includes forming a first electrode having a cylindrical or pillar shape, the first electrode being connected to the switching device.