Abstract: In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.

Abstract: In an integrated circuit, gold interconnect metal lines are electroplated onto plating (Pd) and barrier (TiW) layers, using patterned photoresist. The photoresist is stripped and the plating layer portions thus exposed are etched to expose field areas of the barrier layer. Next, sidewall spacers are formed along each side of the interconnect lines. The field areas of the barrier layer are then etched to isolate the gold interconnect lines. The spacers offset the amount of undercut due to isotropic etching of the TiW barrier metal layer. After etching, the sidewall spacers serve to preserve the as-deposited profile of the gold interconnect lines against breadloafing in a subsequent annealing step.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop (32) and locally oxidizing a P-doped silicon substrate (21) to define a collector region, implanting an N-type collector (43) and diffusing the implants (40, 44). Device emitter, collector and base contact features (64, 66, 68) are photolithographically defined by two openings (54, 56) spaced lengthwise along the collector region. Low resistivity P- and N-type regions (74, 80) are implanted in the substrate in the openings and covered by local oxidation (86, 88). The collector region is preferably formed in a keyhole shape with a wide collector contact feature (66B) and adjoining region 80B and narrow base contact (68B) and emitter (64B) features and intervening region (74B). The substrate (22) is exposed in the emitter and contact features. A single polysilicon layer (94) is deposited, selectively doped and oxidized to form separate base, collector and emitter contacts (94) and a triple diffused NPN transistor (116, 92, 40).

Abstract: An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combination with the parasitic capacitances in the new cell, establishes a time constant sufficient to maintain the state of the secondary nodes during an alpha hit on the primary nodes, so that alpha immunity is achieved without added capacitance. A write boost circuit increases the current in the secondary transistors during a write operation. A memory array is formed of rows of such cells with all of the secondary emitters of each row coupled to a common emitter standby current source.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a collector region. An N-type collector is implanted and the implants are diffused to form a shallow gradient P-N junction. Then, device emitter, base and collector contact features are photolithographically defined by two openings spaced along the length of the collector region. The collector region is formed in a keyhole shape with a wider end portion encompassed by the collector contact feature and adjoining opening and a narrower opposite end portion which includes the base contact and emitter features and intervening opening. Low resistivity P- and N-type regions are implanted in the substrate in the openings; the openings are covered by local oxidation; and the substrate surface region are exposed in the adjoining contact features.

Abstract: In a floating point ALU, a carry-lookahead adder circuit includes integral XOR logic means for complementing the sum bits responsive to an invert signal for generating the absolute value of the difference between two binary operands without added gate delay.

Abstract: In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results.

Abstract: An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier. The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits. A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits. The Z result is stored in a selected one of two accumulators. A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits. Output ports are provided for outputting a selected portion of the accumulator contents. Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a long, narrow collector region. An N-type collector is implanted in the collector region. The implants are diffused to form a shallow gradient P-N junction. Then, device features requiring a predetermined spacing and size are photolithographically defined along the length of the collector region. The device features and the collector region are made long enough for the features to readily transect the collector region even if the mask is misaligned. The active transistor and the collector, base and emitter contacts are self-aligned with the collector region so as to take advantage of the noncritical spacing of the preceding steps. A single polysilicon layer used to form base, collector and emitter contacts and a triple diffusion transistor.

Abstract: A high-speed digital multiplier architecture is implemented in a bipolar very large scale integrated circuit technology. Operand input and product output latches are independently enabled by inverted clock signals. The multiplier can be operated in unclocked, separately clocked and single clock or master-slave modes of operation. The multiplier can be operated to concatenate, rather than multiply, the operands and thereby load the operands directly from the inputs to the output. A selectable format adjust performs a one bit left shift on the product. A low order zero bit is inserted in the shifted product, an overflow flag is set in case the product is -1.0.times.-1.0=1.0, and rounding is correct for both adjusted and unadjusted products. A zero flag is provided which is correct for both rounded and unrounded output products. A negative flag provides an unambiguous indicator of product sign in signed and mixed mode or format adjusted operation.